A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis
On-chip interconnect communication system consists of the drivers, interconnect wires and receivers. Several on-chip communication system models have been developed for the purpose of on-chip fault-tolerant communication research. While most of these models improved the channel modeling, the effects...
| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
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IEEE
2009
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| Online Access: | http://psasir.upm.edu.my/id/eprint/68595/ http://psasir.upm.edu.my/id/eprint/68595/1/A%20process%20variation%20aware%20system-level%20framework%20to%20model%20on-chip%20communication%20system%20in%20support%20of%20fault%20tolerant%20analysis.pdf |
| _version_ | 1848856172082233344 |
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| author | Forooshani, Arash Abtahi Rokhani, Fakhrul Zaman Samsudin, Khairulmizam Abd Aziz, Samsuzana |
| author_facet | Forooshani, Arash Abtahi Rokhani, Fakhrul Zaman Samsudin, Khairulmizam Abd Aziz, Samsuzana |
| author_sort | Forooshani, Arash Abtahi |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | On-chip interconnect communication system consists of the drivers, interconnect wires and receivers. Several on-chip communication system models have been developed for the purpose of on-chip fault-tolerant communication research. While most of these models improved the channel modeling, the effects of the drivers and receivers to the whole communication system were largely ignored. In this paper, we introduce a comprehensive, system-level framework, to capture and integrate the characteristics of the channel as well as the drivers and receivers. The proposed framework offers a methodology to model the on-chip interconnect communication system and can provide a flexible and updateable platform to evaluate fault-tolerant communication approaches. Furthermore, the current deterministic paradigm which end is worst case analysis pessimism is avoided by shifting towards statistical design flow to reduce uncertainties caused by process variation. |
| first_indexed | 2025-11-15T11:37:25Z |
| format | Conference or Workshop Item |
| id | upm-68595 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T11:37:25Z |
| publishDate | 2009 |
| publisher | IEEE |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-685952019-06-10T02:43:38Z http://psasir.upm.edu.my/id/eprint/68595/ A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis Forooshani, Arash Abtahi Rokhani, Fakhrul Zaman Samsudin, Khairulmizam Abd Aziz, Samsuzana On-chip interconnect communication system consists of the drivers, interconnect wires and receivers. Several on-chip communication system models have been developed for the purpose of on-chip fault-tolerant communication research. While most of these models improved the channel modeling, the effects of the drivers and receivers to the whole communication system were largely ignored. In this paper, we introduce a comprehensive, system-level framework, to capture and integrate the characteristics of the channel as well as the drivers and receivers. The proposed framework offers a methodology to model the on-chip interconnect communication system and can provide a flexible and updateable platform to evaluate fault-tolerant communication approaches. Furthermore, the current deterministic paradigm which end is worst case analysis pessimism is avoided by shifting towards statistical design flow to reduce uncertainties caused by process variation. IEEE 2009 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/68595/1/A%20process%20variation%20aware%20system-level%20framework%20to%20model%20on-chip%20communication%20system%20in%20support%20of%20fault%20tolerant%20analysis.pdf Forooshani, Arash Abtahi and Rokhani, Fakhrul Zaman and Samsudin, Khairulmizam and Abd Aziz, Samsuzana (2009) A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis. In: 2009 IEEE Student Conference on Research and Development (SCOReD 2009), 16-18 Nov. 2009, UPM, Serdang, Selangor. (pp. 97-100). 10.1109/SCORED.2009.5443278 |
| spellingShingle | Forooshani, Arash Abtahi Rokhani, Fakhrul Zaman Samsudin, Khairulmizam Abd Aziz, Samsuzana A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis |
| title | A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis |
| title_full | A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis |
| title_fullStr | A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis |
| title_full_unstemmed | A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis |
| title_short | A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis |
| title_sort | process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis |
| url | http://psasir.upm.edu.my/id/eprint/68595/ http://psasir.upm.edu.my/id/eprint/68595/ http://psasir.upm.edu.my/id/eprint/68595/1/A%20process%20variation%20aware%20system-level%20framework%20to%20model%20on-chip%20communication%20system%20in%20support%20of%20fault%20tolerant%20analysis.pdf |