Radio frequency front end receiver blocks with ultra low supply voltage and low power dissipation for Zigbee applications - Tan, Gim Heng (2015)
Portable wireless devices have been the heat of demands in recent years for many applications such as Wireless Sensor Network (WSN) which requires low power consumption since these devices are commonly powered up by battery. One way to reduce circuit power consumption is to lower the supply voltage or DC current of the circuit. Continuous modern technology scaling with a proportional supply voltage reduction outlays a challenge in designing Radio Frequency (RF) circuits. In fact, the recent supply voltage and power consumption for mixer have been saturated at around 0.8V and 1mW respectively. Direct conversion receiver (DCR) is the preferred choice of low power adaptation for the receiver front-end. The most common topologies for mixer are Gilbert cell, folded cascode and current bleeding mixer. However, these architectures still require high supply voltage to operate. The proposed architecture combines the current bleeding technique and folded structure to realize the operation at ultra-low supply voltage of 0.5V while enhancing the isolation between Local Oscillator (LO) and RF ports. This mixer exhibits a measured conversion gain of 11dB at the radio frequency (RF) of 2.4GHz, an input third-order intercept point (IIP3) of -0.4dBm and a LO-RF isolation measured to 60 dB and the DC power consumption is 850μW. This research also includes the design and analysis of current bleeding mixer topology adapting forward body bias technique coupled with the integration of an inductor at the gate of the NMOS bleeding transistor to increase the conversion gain without additional DC power consumption. The measured conversion gain and IIP3 of this mixer is 13dB and -0.5dBm respectively and only consume DC power of 480μw and operates at 0.35V of supply voltage. Integrated LNA-Mixer is investigated in this thesis which focuses on ultra-low voltage and low power implementation. This integrated chip features a simulated conversion gain of 20.3dB at the radio frequency (RF) of 2.4GHz, an input third-order intercept point (IIP3) of -10.3dBm and Noise Figure (NF) is at 7.2dB. The dc power consumption is 950μw while working at the supply voltage of 0.5V. The circuits are designed such that the critical transistors operate at optimum transconductance to meet the low power requirement of ZigBee applications. All circuits were fabricated using CMOS 0.13um technology and measurement was performed on die samples. As a conclusion, the ultra-low voltage and low-power techniques used in this research meets the requirement for ZigBee applications while working at supply voltage of 0.5V and 0.35V with power dissipation of less than 1mW.