Reconfigurable enhanced path metric updater unit for Space Time Trellis Code Viterbi decoder
Space Time Trellis Code (STTC) encoding and decoding techniques are effective for delivery of a reliable information because of the signal to noise ratio is very small. Even though the Viterbi algorithm is complicated to be designed, these methods typically used large memory space to store the infor...
| Main Authors: | , , , , , , |
|---|---|
| Format: | Article |
| Published: |
Penerbit Universiti Teknikal Malaysia Melaka
2017
|
| Online Access: | http://psasir.upm.edu.my/id/eprint/62922/ |
| _version_ | 1848854691060908032 |
|---|---|
| author | Abu, Mohd Azlan Harun, Harlisya Harmin, Mohammad Yazdi Abdul Wahab, Noor Izzri Rahmat, Mohd Khairil Abd Hamid, Mohd Fairuz Ramli, Aizat Faiz |
| author_facet | Abu, Mohd Azlan Harun, Harlisya Harmin, Mohammad Yazdi Abdul Wahab, Noor Izzri Rahmat, Mohd Khairil Abd Hamid, Mohd Fairuz Ramli, Aizat Faiz |
| author_sort | Abu, Mohd Azlan |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | Space Time Trellis Code (STTC) encoding and decoding techniques are effective for delivery of a reliable information because of the signal to noise ratio is very small. Even though the Viterbi algorithm is complicated to be designed, these methods typically used large memory space to store the information that have been processed mainly at the Path Metric Updater (PMU). Therefore, an effective memory management technique is one of the key factors in designing the STTC Viterbi decoder for low power consumption applications. This paper proposed the PMU memory reduction technique especially on Traceback activities that usually required a lot of memories for storing the data that has been processed in the past part by using Altera Quartus 2 and 0.18 µm Altera CPLD 5M570ZF256C5 as targeted hardware. Through this method, the reduction achieved at least 66% of memory requirements and 75% improvements in processing time without a significant effects on the outputs results of the STTC Viterbi Decoder for 4-PSK modulation technique by using 50MHz clocks. |
| first_indexed | 2025-11-15T11:13:53Z |
| format | Article |
| id | upm-62922 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| last_indexed | 2025-11-15T11:13:53Z |
| publishDate | 2017 |
| publisher | Penerbit Universiti Teknikal Malaysia Melaka |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-629222022-11-25T01:34:42Z http://psasir.upm.edu.my/id/eprint/62922/ Reconfigurable enhanced path metric updater unit for Space Time Trellis Code Viterbi decoder Abu, Mohd Azlan Harun, Harlisya Harmin, Mohammad Yazdi Abdul Wahab, Noor Izzri Rahmat, Mohd Khairil Abd Hamid, Mohd Fairuz Ramli, Aizat Faiz Space Time Trellis Code (STTC) encoding and decoding techniques are effective for delivery of a reliable information because of the signal to noise ratio is very small. Even though the Viterbi algorithm is complicated to be designed, these methods typically used large memory space to store the information that have been processed mainly at the Path Metric Updater (PMU). Therefore, an effective memory management technique is one of the key factors in designing the STTC Viterbi decoder for low power consumption applications. This paper proposed the PMU memory reduction technique especially on Traceback activities that usually required a lot of memories for storing the data that has been processed in the past part by using Altera Quartus 2 and 0.18 µm Altera CPLD 5M570ZF256C5 as targeted hardware. Through this method, the reduction achieved at least 66% of memory requirements and 75% improvements in processing time without a significant effects on the outputs results of the STTC Viterbi Decoder for 4-PSK modulation technique by using 50MHz clocks. Penerbit Universiti Teknikal Malaysia Melaka 2017-09 Article PeerReviewed Abu, Mohd Azlan and Harun, Harlisya and Harmin, Mohammad Yazdi and Abdul Wahab, Noor Izzri and Rahmat, Mohd Khairil and Abd Hamid, Mohd Fairuz and Ramli, Aizat Faiz (2017) Reconfigurable enhanced path metric updater unit for Space Time Trellis Code Viterbi decoder. Journal of Telecommunication, Electronic and Computer Engineering, 9 (2-7). 49 - 53. ISSN 2180-1843; ESSN: 2289-8131 https://jtec.utem.edu.my/jtec/article/view/2591 |
| spellingShingle | Abu, Mohd Azlan Harun, Harlisya Harmin, Mohammad Yazdi Abdul Wahab, Noor Izzri Rahmat, Mohd Khairil Abd Hamid, Mohd Fairuz Ramli, Aizat Faiz Reconfigurable enhanced path metric updater unit for Space Time Trellis Code Viterbi decoder |
| title | Reconfigurable enhanced path metric updater unit for Space Time Trellis Code Viterbi decoder |
| title_full | Reconfigurable enhanced path metric updater unit for Space Time Trellis Code Viterbi decoder |
| title_fullStr | Reconfigurable enhanced path metric updater unit for Space Time Trellis Code Viterbi decoder |
| title_full_unstemmed | Reconfigurable enhanced path metric updater unit for Space Time Trellis Code Viterbi decoder |
| title_short | Reconfigurable enhanced path metric updater unit for Space Time Trellis Code Viterbi decoder |
| title_sort | reconfigurable enhanced path metric updater unit for space time trellis code viterbi decoder |
| url | http://psasir.upm.edu.my/id/eprint/62922/ http://psasir.upm.edu.my/id/eprint/62922/ |