APA (7th ed.) Citation

Al-Hussaini, K. T. M., Mohd Ali, B., Varahram, P., Hashim, S. J., & Farrell, R. (2017). Hardware co-simulation for a low complexity PAPR reduction scheme on an FPGA. Inderscience.

Chicago Style (17th ed.) Citation

Al-Hussaini, Khalid Taher Mohammed, Borhanuddin Mohd Ali, Pooria Varahram, Shaiful Jahari Hashim, and Ronan Farrell. Hardware Co-simulation for a Low Complexity PAPR Reduction Scheme on an FPGA. Inderscience, 2017.

MLA (9th ed.) Citation

Al-Hussaini, Khalid Taher Mohammed, et al. Hardware Co-simulation for a Low Complexity PAPR Reduction Scheme on an FPGA. Inderscience, 2017.