CMOS technology for increasing efficiency of clock gating techniques using tri-state buffer
Clock gating is an effective technique of decreasing dynamic power dissipation in synchronous design. One of the methods used to realize this goal is to mask the clock which goes to the unnecessary to use in specific time. This paper will present a comparative analysis of this clock gating technique...
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| Format: | Article |
| Language: | English |
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Institute of Research and Development, Walailak University
2017
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| Online Access: | http://psasir.upm.edu.my/id/eprint/61131/ http://psasir.upm.edu.my/id/eprint/61131/1/CMOS%20technology%20for%20increasing%20efficiency%20of%20clock%20gating%20techniques%20using%20tri-state%20buffer.pdf |
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| author | Mohammed, Maan Hameed Mohamed Khmag, Asem Ib. Rokhani, Fakhrul Zaman Ramli, Abd Rahman |
| author_facet | Mohammed, Maan Hameed Mohamed Khmag, Asem Ib. Rokhani, Fakhrul Zaman Ramli, Abd Rahman |
| author_sort | Mohammed, Maan Hameed |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | Clock gating is an effective technique of decreasing dynamic power dissipation in synchronous design. One of the methods used to realize this goal is to mask the clock which goes to the unnecessary to use in specific time. This paper will present a comparative analysis of this clock gating technique in an 8-bit Arithmetic Logic Unit (ALU). The new clock gating method provides a solution to the problems in the existing techniques. The new proposed clock gating technique generating circuit uses tri-state buffer in a negative latch design, instead of OR gate logic. With the same function being performed, this circuit saves more power and reduces area used, irrespective of design performance. The minimum power gain realized 6.4 % percentage in total power consumption by executing 20 MHz frequency. It also used a 0.9 % occupation area. The proposed method was implemented by using ASIC design methodology, and 130 nm standard cell technology libraries were used for ASIC implementation. Furthermore, the architecture of the ALU was created using Verilog HDL language (32-Bit Quartus II 11.1 Web Edition). The simulation was carried out by using the Model Sim-Altera 10.0c (Quartus II 11.1 Starter Edition). Finally, the design will reduce complexity in hardware and similar clock power. |
| first_indexed | 2025-11-15T11:08:24Z |
| format | Article |
| id | upm-61131 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T11:08:24Z |
| publishDate | 2017 |
| publisher | Institute of Research and Development, Walailak University |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-611312018-09-14T03:46:08Z http://psasir.upm.edu.my/id/eprint/61131/ CMOS technology for increasing efficiency of clock gating techniques using tri-state buffer Mohammed, Maan Hameed Mohamed Khmag, Asem Ib. Rokhani, Fakhrul Zaman Ramli, Abd Rahman Clock gating is an effective technique of decreasing dynamic power dissipation in synchronous design. One of the methods used to realize this goal is to mask the clock which goes to the unnecessary to use in specific time. This paper will present a comparative analysis of this clock gating technique in an 8-bit Arithmetic Logic Unit (ALU). The new clock gating method provides a solution to the problems in the existing techniques. The new proposed clock gating technique generating circuit uses tri-state buffer in a negative latch design, instead of OR gate logic. With the same function being performed, this circuit saves more power and reduces area used, irrespective of design performance. The minimum power gain realized 6.4 % percentage in total power consumption by executing 20 MHz frequency. It also used a 0.9 % occupation area. The proposed method was implemented by using ASIC design methodology, and 130 nm standard cell technology libraries were used for ASIC implementation. Furthermore, the architecture of the ALU was created using Verilog HDL language (32-Bit Quartus II 11.1 Web Edition). The simulation was carried out by using the Model Sim-Altera 10.0c (Quartus II 11.1 Starter Edition). Finally, the design will reduce complexity in hardware and similar clock power. Institute of Research and Development, Walailak University 2017 Article PeerReviewed text en http://psasir.upm.edu.my/id/eprint/61131/1/CMOS%20technology%20for%20increasing%20efficiency%20of%20clock%20gating%20techniques%20using%20tri-state%20buffer.pdf Mohammed, Maan Hameed and Mohamed Khmag, Asem Ib. and Rokhani, Fakhrul Zaman and Ramli, Abd Rahman (2017) CMOS technology for increasing efficiency of clock gating techniques using tri-state buffer. Walailak Journal of Science and Technology, 14 (4). pp. 327-338. ISSN 1686-3933; ESSN: 2228-835X http://wjst.wu.ac.th |
| spellingShingle | Mohammed, Maan Hameed Mohamed Khmag, Asem Ib. Rokhani, Fakhrul Zaman Ramli, Abd Rahman CMOS technology for increasing efficiency of clock gating techniques using tri-state buffer |
| title | CMOS technology for increasing efficiency of clock gating techniques using tri-state buffer |
| title_full | CMOS technology for increasing efficiency of clock gating techniques using tri-state buffer |
| title_fullStr | CMOS technology for increasing efficiency of clock gating techniques using tri-state buffer |
| title_full_unstemmed | CMOS technology for increasing efficiency of clock gating techniques using tri-state buffer |
| title_short | CMOS technology for increasing efficiency of clock gating techniques using tri-state buffer |
| title_sort | cmos technology for increasing efficiency of clock gating techniques using tri-state buffer |
| url | http://psasir.upm.edu.my/id/eprint/61131/ http://psasir.upm.edu.my/id/eprint/61131/ http://psasir.upm.edu.my/id/eprint/61131/1/CMOS%20technology%20for%20increasing%20efficiency%20of%20clock%20gating%20techniques%20using%20tri-state%20buffer.pdf |