APA (7th ed.) Citation

Masoumidezfouli, S., Syed Mohamed, S. A. R. A., & Rokhani, F. Z. (2017). New tool for converting high-level representations of finite state machines to verilog HDL. IEEE.

Chicago Style (17th ed.) Citation

Masoumidezfouli, Seyedhossein, Syed Abdul Rahman Al-Haddad Syed Mohamed, and Fakhrul Zaman Rokhani. New Tool for Converting High-level Representations of Finite State Machines to Verilog HDL. IEEE, 2017.

MLA (9th ed.) Citation

Masoumidezfouli, Seyedhossein, et al. New Tool for Converting High-level Representations of Finite State Machines to Verilog HDL. IEEE, 2017.