Analog signal path circuit for a four transistor pixel in standard 0.13μm CMOS technology
This project is aimed to develop the layout for the analog signal path of a 4 transistor pixel CMOS image sensor using EDA tools in standard 0.13μm Silterra fabrication technology. The sub-circuit blocks that define the analog input-output path consists of the 320×240 pixel array, 320 column paralle...
| Main Authors: | , , , , |
|---|---|
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2017
|
| Online Access: | http://psasir.upm.edu.my/id/eprint/59445/ http://psasir.upm.edu.my/id/eprint/59445/1/Analog%20signal%20path%20circuit%20for%20a%20four%20transistor%20pixel%20in%20standard%200.13%CE%BCm%20CMOS%20technology.pdf |
| _version_ | 1848853922859450368 |
|---|---|
| author | Shafie, Suhaidi Md Yunus, Nurul Amziah Ong, Wei Chiek Wang, Chee Yew Abdul Halin, Izhal |
| author_facet | Shafie, Suhaidi Md Yunus, Nurul Amziah Ong, Wei Chiek Wang, Chee Yew Abdul Halin, Izhal |
| author_sort | Shafie, Suhaidi |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | This project is aimed to develop the layout for the analog signal path of a 4 transistor pixel CMOS image sensor using EDA tools in standard 0.13μm Silterra fabrication technology. The sub-circuit blocks that define the analog input-output path consists of the 320×240 pixel array, 320 column parallel correlated double sampling circuits, an output buffer amplifier and all associated bias circuitry. Each pixel size has a dimension of 10μm × 10μm. The pixel's frame rate is targeted to be 120 frames per second (fps) working in a QVGA picture format (320× 240 pixels). From simulation, the illumination range of 0.01 lux to 0.25 lux has been tested and shows only a 2.8% error from the ideal output linearity. |
| first_indexed | 2025-11-15T11:01:40Z |
| format | Conference or Workshop Item |
| id | upm-59445 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T11:01:40Z |
| publishDate | 2017 |
| publisher | IEEE |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-594452018-03-05T07:12:59Z http://psasir.upm.edu.my/id/eprint/59445/ Analog signal path circuit for a four transistor pixel in standard 0.13μm CMOS technology Shafie, Suhaidi Md Yunus, Nurul Amziah Ong, Wei Chiek Wang, Chee Yew Abdul Halin, Izhal This project is aimed to develop the layout for the analog signal path of a 4 transistor pixel CMOS image sensor using EDA tools in standard 0.13μm Silterra fabrication technology. The sub-circuit blocks that define the analog input-output path consists of the 320×240 pixel array, 320 column parallel correlated double sampling circuits, an output buffer amplifier and all associated bias circuitry. Each pixel size has a dimension of 10μm × 10μm. The pixel's frame rate is targeted to be 120 frames per second (fps) working in a QVGA picture format (320× 240 pixels). From simulation, the illumination range of 0.01 lux to 0.25 lux has been tested and shows only a 2.8% error from the ideal output linearity. IEEE 2017 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/59445/1/Analog%20signal%20path%20circuit%20for%20a%20four%20transistor%20pixel%20in%20standard%200.13%CE%BCm%20CMOS%20technology.pdf Shafie, Suhaidi and Md Yunus, Nurul Amziah and Ong, Wei Chiek and Wang, Chee Yew and Abdul Halin, Izhal (2017) Analog signal path circuit for a four transistor pixel in standard 0.13μm CMOS technology. In: 2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 31 Oct.-2 Nov. 2017, Kuala Lumpur, Malaysia. (pp. 133-136). 10.1109/PRIMEASIA.2017.8280382 |
| spellingShingle | Shafie, Suhaidi Md Yunus, Nurul Amziah Ong, Wei Chiek Wang, Chee Yew Abdul Halin, Izhal Analog signal path circuit for a four transistor pixel in standard 0.13μm CMOS technology |
| title | Analog signal path circuit for a four transistor pixel in standard 0.13μm CMOS technology |
| title_full | Analog signal path circuit for a four transistor pixel in standard 0.13μm CMOS technology |
| title_fullStr | Analog signal path circuit for a four transistor pixel in standard 0.13μm CMOS technology |
| title_full_unstemmed | Analog signal path circuit for a four transistor pixel in standard 0.13μm CMOS technology |
| title_short | Analog signal path circuit for a four transistor pixel in standard 0.13μm CMOS technology |
| title_sort | analog signal path circuit for a four transistor pixel in standard 0.13μm cmos technology |
| url | http://psasir.upm.edu.my/id/eprint/59445/ http://psasir.upm.edu.my/id/eprint/59445/ http://psasir.upm.edu.my/id/eprint/59445/1/Analog%20signal%20path%20circuit%20for%20a%20four%20transistor%20pixel%20in%20standard%200.13%CE%BCm%20CMOS%20technology.pdf |