Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip
In this paper, the FPGA architecture having a hardwired network-on-chip (NoC) as system-level interconnect resource with adaptive router to support ranges of traffic condition. The proposed adaptive routers cooperatively allocate the virtual channel to minimizes the cost of supporting a wide range o...
| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2016
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| Online Access: | http://psasir.upm.edu.my/id/eprint/59421/ http://psasir.upm.edu.my/id/eprint/59421/1/Cooperative%20virtual%20channel%20router%20for%20adaptive%20hardwired%20FPGA%20network-on-chip.pdf |
| Summary: | In this paper, the FPGA architecture having a hardwired network-on-chip (NoC) as system-level interconnect resource with adaptive router to support ranges of traffic condition. The proposed adaptive routers cooperatively allocate the virtual channel to minimizes the cost of supporting a wide range of traffic requirements from various FPGA application design instances. Simulation results show performance augmentation of 25% on average over an equal-size standard router, or achieve iso-performance using 50% less virtual channel buffer size. |
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