Cost-efficient standard cell library timing and power validation techniques
A standard cell library contains functional blocks with known electrical characteristics,which are characterized to obtain the following parameters: propagation delay, output transition time, power representation, and capacitance. Standard cell libraries are widely applied by industry designers to t...
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| Format: | Thesis |
| Language: | English |
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2015
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| Online Access: | http://psasir.upm.edu.my/id/eprint/56224/ http://psasir.upm.edu.my/id/eprint/56224/1/FK%202015%2025.pdf |
| _version_ | 1848853022511202304 |
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| author | Al-Frajat, Jaafar Khadair Kadam |
| author_facet | Al-Frajat, Jaafar Khadair Kadam |
| author_sort | Al-Frajat, Jaafar Khadair Kadam |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | A standard cell library contains functional blocks with known electrical characteristics,which are characterized to obtain the following parameters: propagation delay, output transition time, power representation, and capacitance. Standard cell libraries are widely applied by industry designers to the implementation of application-specific integrated circuit (ASIC) designs. Such application is facilitated by the provision of extremely high gate density and excellent electrical performance. Early validation of the characterization data for the standard cells on physical silicon is required to guarantee the correct implementation of the final design in silicon functions. The silicon validation processes correlate the characterized values with the actual silicon performance. However, this process is costly in terms of design and fabrication. Moreover, testing the process on wafer silicon measurement validation is difficult in terms of test time and because of equipment limitation. In this research, an enhanced silicon validation method was developed to validate the libraries using the basics of the delay chain technique. The method was tested by applying two new approaches to designing test element group (TEG) circuits. These two approaches are sharing load between multi-chains and input control for multi-input gates. These proposed methods can reduce the cost of fabrication through total silicon area reduction of the test chip achieved by decreasing the total number of transistors required in the design. The total number of I/O PADs required in the validation process can also be reduced, and the test time can be enhanced. The effectiveness of our proposed approaches was evaluated on several test chips that consist of an inverter, a multi-input NAND, and NOR gates as basic cells of combinational logic circuits in the library. Test chips were designed to verify the functionality of the design and to validate timing delays and dynamic and leakage power, which are influenced by cell output loading and cell input transition parameters. The test chip was tested at operating environments that match simulation corners to cover datasheet-specified operating conditions. |
| first_indexed | 2025-11-15T10:47:22Z |
| format | Thesis |
| id | upm-56224 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T10:47:22Z |
| publishDate | 2015 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-562242024-10-21T01:41:03Z http://psasir.upm.edu.my/id/eprint/56224/ Cost-efficient standard cell library timing and power validation techniques Al-Frajat, Jaafar Khadair Kadam A standard cell library contains functional blocks with known electrical characteristics,which are characterized to obtain the following parameters: propagation delay, output transition time, power representation, and capacitance. Standard cell libraries are widely applied by industry designers to the implementation of application-specific integrated circuit (ASIC) designs. Such application is facilitated by the provision of extremely high gate density and excellent electrical performance. Early validation of the characterization data for the standard cells on physical silicon is required to guarantee the correct implementation of the final design in silicon functions. The silicon validation processes correlate the characterized values with the actual silicon performance. However, this process is costly in terms of design and fabrication. Moreover, testing the process on wafer silicon measurement validation is difficult in terms of test time and because of equipment limitation. In this research, an enhanced silicon validation method was developed to validate the libraries using the basics of the delay chain technique. The method was tested by applying two new approaches to designing test element group (TEG) circuits. These two approaches are sharing load between multi-chains and input control for multi-input gates. These proposed methods can reduce the cost of fabrication through total silicon area reduction of the test chip achieved by decreasing the total number of transistors required in the design. The total number of I/O PADs required in the validation process can also be reduced, and the test time can be enhanced. The effectiveness of our proposed approaches was evaluated on several test chips that consist of an inverter, a multi-input NAND, and NOR gates as basic cells of combinational logic circuits in the library. Test chips were designed to verify the functionality of the design and to validate timing delays and dynamic and leakage power, which are influenced by cell output loading and cell input transition parameters. The test chip was tested at operating environments that match simulation corners to cover datasheet-specified operating conditions. 2015-07 Thesis NonPeerReviewed text en http://psasir.upm.edu.my/id/eprint/56224/1/FK%202015%2025.pdf Al-Frajat, Jaafar Khadair Kadam (2015) Cost-efficient standard cell library timing and power validation techniques. Masters thesis, Universiti Putra Malaysia. Digital integrated circuits - Design and construction Application-specific integrated circuits |
| spellingShingle | Digital integrated circuits - Design and construction Application-specific integrated circuits Al-Frajat, Jaafar Khadair Kadam Cost-efficient standard cell library timing and power validation techniques |
| title | Cost-efficient standard cell library timing and power validation techniques |
| title_full | Cost-efficient standard cell library timing and power validation techniques |
| title_fullStr | Cost-efficient standard cell library timing and power validation techniques |
| title_full_unstemmed | Cost-efficient standard cell library timing and power validation techniques |
| title_short | Cost-efficient standard cell library timing and power validation techniques |
| title_sort | cost-efficient standard cell library timing and power validation techniques |
| topic | Digital integrated circuits - Design and construction Application-specific integrated circuits |
| url | http://psasir.upm.edu.my/id/eprint/56224/ http://psasir.upm.edu.my/id/eprint/56224/1/FK%202015%2025.pdf |