Voltage notch analysis of a taps-based multilevel inverter in the event of one switch failure
There are many advantages of the cascaded multilevel inverter such as low voltage stress for each switching device and higher power quality. One of the drawbacks for this type of inverter is the series switching of the cells it used in its operation. In order to properly operate, all switches must b...
| Main Authors: | , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2015
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| Online Access: | http://psasir.upm.edu.my/id/eprint/56095/ http://psasir.upm.edu.my/id/eprint/56095/1/Voltage%20notch%20analysis%20of%20a%20taps-based%20multilevel%20inverter%20in%20the%20event%20of%20one%20switch%20failure.pdf |
| _version_ | 1848852985777487872 |
|---|---|
| author | Mohamad, Ahmad Syukri Mariun, Norman |
| author_facet | Mohamad, Ahmad Syukri Mariun, Norman |
| author_sort | Mohamad, Ahmad Syukri |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | There are many advantages of the cascaded multilevel inverter such as low voltage stress for each switching device and higher power quality. One of the drawbacks for this type of inverter is the series switching of the cells it used in its operation. In order to properly operate, all switches must be operational; failure of only one of the switches will result in the failure of the inverter operation. This can be clearly seen in the case of cascaded H-bridge multilevel inverter and other topologies derived from it. In this paper a series cascaded cells taps-based multilevel inverter topology with a minimum number of switching devices and driver circuits needed is discussed. The voltage taps-based topology also needs to turn on only three switching devices at any operation time for any output voltage level configurations. The failure of one of the switches on this topology does not cause total malfunction of the inverter, instead it only causes voltage notches to form on the resulting sine wave output. The notch effect is verified by the experimental results of a prototype single phase 41-level inverter. |
| first_indexed | 2025-11-15T10:46:47Z |
| format | Conference or Workshop Item |
| id | upm-56095 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T10:46:47Z |
| publishDate | 2015 |
| publisher | IEEE |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-560952017-07-03T09:34:34Z http://psasir.upm.edu.my/id/eprint/56095/ Voltage notch analysis of a taps-based multilevel inverter in the event of one switch failure Mohamad, Ahmad Syukri Mariun, Norman There are many advantages of the cascaded multilevel inverter such as low voltage stress for each switching device and higher power quality. One of the drawbacks for this type of inverter is the series switching of the cells it used in its operation. In order to properly operate, all switches must be operational; failure of only one of the switches will result in the failure of the inverter operation. This can be clearly seen in the case of cascaded H-bridge multilevel inverter and other topologies derived from it. In this paper a series cascaded cells taps-based multilevel inverter topology with a minimum number of switching devices and driver circuits needed is discussed. The voltage taps-based topology also needs to turn on only three switching devices at any operation time for any output voltage level configurations. The failure of one of the switches on this topology does not cause total malfunction of the inverter, instead it only causes voltage notches to form on the resulting sine wave output. The notch effect is verified by the experimental results of a prototype single phase 41-level inverter. IEEE 2015 Conference or Workshop Item PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/56095/1/Voltage%20notch%20analysis%20of%20a%20taps-based%20multilevel%20inverter%20in%20the%20event%20of%20one%20switch%20failure.pdf Mohamad, Ahmad Syukri and Mariun, Norman (2015) Voltage notch analysis of a taps-based multilevel inverter in the event of one switch failure. In: 2015 IEEE 3rd International Conference on Smart Instrumentation, Measurement and Applications (ICSIMA 2015), 24-25 Nov. 2015, Putrajaya, Malaysia. . 10.1109/ICSIMA.2015.7559017 |
| spellingShingle | Mohamad, Ahmad Syukri Mariun, Norman Voltage notch analysis of a taps-based multilevel inverter in the event of one switch failure |
| title | Voltage notch analysis of a taps-based multilevel inverter in the event of one switch failure |
| title_full | Voltage notch analysis of a taps-based multilevel inverter in the event of one switch failure |
| title_fullStr | Voltage notch analysis of a taps-based multilevel inverter in the event of one switch failure |
| title_full_unstemmed | Voltage notch analysis of a taps-based multilevel inverter in the event of one switch failure |
| title_short | Voltage notch analysis of a taps-based multilevel inverter in the event of one switch failure |
| title_sort | voltage notch analysis of a taps-based multilevel inverter in the event of one switch failure |
| url | http://psasir.upm.edu.my/id/eprint/56095/ http://psasir.upm.edu.my/id/eprint/56095/ http://psasir.upm.edu.my/id/eprint/56095/1/Voltage%20notch%20analysis%20of%20a%20taps-based%20multilevel%20inverter%20in%20the%20event%20of%20one%20switch%20failure.pdf |