Simulation of a 41-level inverter built by cascading two symmetric cascaded multilevel inverter
The main disadvantage for cascaded multilevel inverter is the high number of switching device it needs in an installation. To reduce total harmonics distortion (THD) of the output waveform, the number of output voltage level has to be increased, hence the higher number of switching devices. This con...
| Main Authors: | , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2016
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| Online Access: | http://psasir.upm.edu.my/id/eprint/56004/ http://psasir.upm.edu.my/id/eprint/56004/1/Simulation%20of%20a%2041-level%20inverter%20built%20by%20cascading%20two%20symmetric%20cascaded%20multilevel%20inverter.pdf |
| _version_ | 1848852960010829824 |
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| author | Mohamad, Ahmad Syukri Mariun, Norman |
| author_facet | Mohamad, Ahmad Syukri Mariun, Norman |
| author_sort | Mohamad, Ahmad Syukri |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | The main disadvantage for cascaded multilevel inverter is the high number of switching device it needs in an installation. To reduce total harmonics distortion (THD) of the output waveform, the number of output voltage level has to be increased, hence the higher number of switching devices. This consequently increases the installation cost, inverter size and voltage losses at the load terminals. In this paper a new cascaded multilevel inverter concept is proposed with a small number of switching devices and dc sources needed. The 41-level inverter consist of several high voltage and low voltage dc sources. The switching strategy of the inverter is the low voltage dc sources are switched in several times in a half cycle of the output. The 41-level cascaded multilevel inverter operation is then demonstrated by the Matlab simulation. |
| first_indexed | 2025-11-15T10:46:22Z |
| format | Conference or Workshop Item |
| id | upm-56004 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T10:46:22Z |
| publishDate | 2016 |
| publisher | IEEE |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-560042017-07-03T09:28:12Z http://psasir.upm.edu.my/id/eprint/56004/ Simulation of a 41-level inverter built by cascading two symmetric cascaded multilevel inverter Mohamad, Ahmad Syukri Mariun, Norman The main disadvantage for cascaded multilevel inverter is the high number of switching device it needs in an installation. To reduce total harmonics distortion (THD) of the output waveform, the number of output voltage level has to be increased, hence the higher number of switching devices. This consequently increases the installation cost, inverter size and voltage losses at the load terminals. In this paper a new cascaded multilevel inverter concept is proposed with a small number of switching devices and dc sources needed. The 41-level inverter consist of several high voltage and low voltage dc sources. The switching strategy of the inverter is the low voltage dc sources are switched in several times in a half cycle of the output. The 41-level cascaded multilevel inverter operation is then demonstrated by the Matlab simulation. IEEE 2016 Conference or Workshop Item PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/56004/1/Simulation%20of%20a%2041-level%20inverter%20built%20by%20cascading%20two%20symmetric%20cascaded%20multilevel%20inverter.pdf Mohamad, Ahmad Syukri and Mariun, Norman (2016) Simulation of a 41-level inverter built by cascading two symmetric cascaded multilevel inverter. In: 2016 7th IEEE Control and System Graduate Research Colloquium (ICSGRC 2016), 8 Aug. 2016, UiTM Shah Alam, Selangor, Malaysia. (pp. 12-16). 10.1109/ICSGRC.2016.7813293 |
| spellingShingle | Mohamad, Ahmad Syukri Mariun, Norman Simulation of a 41-level inverter built by cascading two symmetric cascaded multilevel inverter |
| title | Simulation of a 41-level inverter built by cascading two symmetric cascaded multilevel inverter |
| title_full | Simulation of a 41-level inverter built by cascading two symmetric cascaded multilevel inverter |
| title_fullStr | Simulation of a 41-level inverter built by cascading two symmetric cascaded multilevel inverter |
| title_full_unstemmed | Simulation of a 41-level inverter built by cascading two symmetric cascaded multilevel inverter |
| title_short | Simulation of a 41-level inverter built by cascading two symmetric cascaded multilevel inverter |
| title_sort | simulation of a 41-level inverter built by cascading two symmetric cascaded multilevel inverter |
| url | http://psasir.upm.edu.my/id/eprint/56004/ http://psasir.upm.edu.my/id/eprint/56004/ http://psasir.upm.edu.my/id/eprint/56004/1/Simulation%20of%20a%2041-level%20inverter%20built%20by%20cascading%20two%20symmetric%20cascaded%20multilevel%20inverter.pdf |