Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications

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Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship betwee...

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Bibliographic Details
Main Authors:	Abdulrazzaq, Bilal Isam, Ibrahim, Omar J., Kawahito, Shoji, Mohd Sidek, Roslina, Shafie, Suhaidi, Md Yunus, Nurul Amziah, Lee, Lini, Abdul Halin, Izhal
Format:	Article
Language:	English
Published:	MDPI 2016
Online Access:	http://psasir.upm.edu.my/id/eprint/55975/ http://psasir.upm.edu.my/id/eprint/55975/1/55975.pdf

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