Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications
A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship betwee...
| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI
2016
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| Online Access: | http://psasir.upm.edu.my/id/eprint/55975/ http://psasir.upm.edu.my/id/eprint/55975/1/55975.pdf |
| _version_ | 1848852952172724224 |
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| author | Abdulrazzaq, Bilal Isam Ibrahim, Omar J. Kawahito, Shoji Mohd Sidek, Roslina Shafie, Suhaidi Md Yunus, Nurul Amziah Lee, Lini Abdul Halin, Izhal |
| author_facet | Abdulrazzaq, Bilal Isam Ibrahim, Omar J. Kawahito, Shoji Mohd Sidek, Roslina Shafie, Suhaidi Md Yunus, Nurul Amziah Lee, Lini Abdul Halin, Izhal |
| author_sort | Abdulrazzaq, Bilal Isam |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL’s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 μm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture’s circuit is 0.1 mW when the DLL is operated at 2 GHz. |
| first_indexed | 2025-11-15T10:46:15Z |
| format | Article |
| id | upm-55975 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T10:46:15Z |
| publishDate | 2016 |
| publisher | MDPI |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-559752017-07-03T09:25:42Z http://psasir.upm.edu.my/id/eprint/55975/ Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications Abdulrazzaq, Bilal Isam Ibrahim, Omar J. Kawahito, Shoji Mohd Sidek, Roslina Shafie, Suhaidi Md Yunus, Nurul Amziah Lee, Lini Abdul Halin, Izhal A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL’s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 μm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture’s circuit is 0.1 mW when the DLL is operated at 2 GHz. MDPI 2016 Article PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/55975/1/55975.pdf Abdulrazzaq, Bilal Isam and Ibrahim, Omar J. and Kawahito, Shoji and Mohd Sidek, Roslina and Shafie, Suhaidi and Md Yunus, Nurul Amziah and Lee, Lini and Abdul Halin, Izhal (2016) Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications. Sensors, 16 (10). art. no. 1593. pp. 1-15. ISSN 1424-8220 http://www.mdpi.com/1424-8220/16/10/1593 10.3390/s16101593 |
| spellingShingle | Abdulrazzaq, Bilal Isam Ibrahim, Omar J. Kawahito, Shoji Mohd Sidek, Roslina Shafie, Suhaidi Md Yunus, Nurul Amziah Lee, Lini Abdul Halin, Izhal Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications |
| title | Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications |
| title_full | Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications |
| title_fullStr | Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications |
| title_full_unstemmed | Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications |
| title_short | Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications |
| title_sort | design of a sub-picosecond jitter with adjustable-range cmos delay-locked loop for high-speed and low-power applications |
| url | http://psasir.upm.edu.my/id/eprint/55975/ http://psasir.upm.edu.my/id/eprint/55975/ http://psasir.upm.edu.my/id/eprint/55975/ http://psasir.upm.edu.my/id/eprint/55975/1/55975.pdf |