Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications
A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship betwee...
| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI
2016
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| Online Access: | http://psasir.upm.edu.my/id/eprint/55975/ http://psasir.upm.edu.my/id/eprint/55975/1/55975.pdf |
| Summary: | A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL’s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 μm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture’s circuit is 0.1 mW when the DLL is operated at 2 GHz. |
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