Sub-picosecond jitter resolution wide range digital delay line for SoC integration

Sub-picosecond jitter resolution wide range digital delay line for SoC integration

A novel three-stage architecture programmable digital delay line (DDL) with a picosecond resolution, 1μs range, and sub-picosecond jitter performance is proposed. Through circuit simulation, a dynamic range of 1μs is obtained in the first stage using 10-bit counters operating at a frequency of 1 GHz...

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Bibliographic Details
Main Authors: Abdulrazzaq, Bilal Isam, Abdul Halin, Izhal, Mohd Sidek, Roslina, Shafie, Suhaidi, Md Yunus, Nurul Amziah, Kawahito, Shoji
Format: Conference or Workshop Item
Language:English
Published: IEEE 2015
Online Access:http://psasir.upm.edu.my/id/eprint/55971/
http://psasir.upm.edu.my/id/eprint/55971/1/Sub-picosecond%20jitter%20resolution%20wide%20range%20digital%20delay%20line%20for%20SoC%20integration.pdf

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