A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability
A programmable CMOS delay line circuit with microsecond delay range and adjustable duty cycle is proposed. Through circuit simulation, approximately 2µs delay range can be achieved using 10-bit counter operating at a clock frequency of 500MHz. Utilising synchronous counters instead of synchronous la...
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| Format: | Article |
| Language: | English |
| Published: |
Universiti Putra Malaysia Press
2017
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| Online Access: | http://psasir.upm.edu.my/id/eprint/55852/ http://psasir.upm.edu.my/id/eprint/55852/1/15-JTS%28S%29-0129-2016-4thProof.pdf |
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| author | Abdulrazzaq, Bilal Isam Abdul Halin, Izhal Lee, Lini Mohd Sidek, Roslina Md Yunus, Nurul Amziah |
| author_facet | Abdulrazzaq, Bilal Isam Abdul Halin, Izhal Lee, Lini Mohd Sidek, Roslina Md Yunus, Nurul Amziah |
| author_sort | Abdulrazzaq, Bilal Isam |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | A programmable CMOS delay line circuit with microsecond delay range and adjustable duty cycle is proposed. Through circuit simulation, approximately 2µs delay range can be achieved using 10-bit counter operating at a clock frequency of 500MHz. Utilising synchronous counters instead of synchronous latches has significantly reduced the large occupied active silicon area as well as the huge power consumption. The generated coarse time delay has shown excellent linearity and immunity to PVT variations. The proposed CMOS delay line is designed using a standard 0.13µm Silterra CMOS technology. The active layout area is (101 x 142) µm2, and the total power consumption is only 0.1 µW. |
| first_indexed | 2025-11-15T10:45:42Z |
| format | Article |
| id | upm-55852 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T10:45:42Z |
| publishDate | 2017 |
| publisher | Universiti Putra Malaysia Press |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-558522017-07-05T03:44:19Z http://psasir.upm.edu.my/id/eprint/55852/ A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability Abdulrazzaq, Bilal Isam Abdul Halin, Izhal Lee, Lini Mohd Sidek, Roslina Md Yunus, Nurul Amziah A programmable CMOS delay line circuit with microsecond delay range and adjustable duty cycle is proposed. Through circuit simulation, approximately 2µs delay range can be achieved using 10-bit counter operating at a clock frequency of 500MHz. Utilising synchronous counters instead of synchronous latches has significantly reduced the large occupied active silicon area as well as the huge power consumption. The generated coarse time delay has shown excellent linearity and immunity to PVT variations. The proposed CMOS delay line is designed using a standard 0.13µm Silterra CMOS technology. The active layout area is (101 x 142) µm2, and the total power consumption is only 0.1 µW. Universiti Putra Malaysia Press 2017 Article PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/55852/1/15-JTS%28S%29-0129-2016-4thProof.pdf Abdulrazzaq, Bilal Isam and Abdul Halin, Izhal and Lee, Lini and Mohd Sidek, Roslina and Md Yunus, Nurul Amziah (2017) A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability. Pertanika Journal of Science & Technology, 25 (spec. Feb.). pp. 123-132. ISSN 0128-7680; ESSN: 2231-8526 http://www.pertanika.upm.edu.my/Pertanika%20PAPERS/JST%20Vol.%2025%20(S)%20Feb.%202017/15-JTS(S)-0129-2016-4thProof.pdf |
| spellingShingle | Abdulrazzaq, Bilal Isam Abdul Halin, Izhal Lee, Lini Mohd Sidek, Roslina Md Yunus, Nurul Amziah A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability |
| title | A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability |
| title_full | A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability |
| title_fullStr | A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability |
| title_full_unstemmed | A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability |
| title_short | A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability |
| title_sort | programmable cmos delay line for wide delay range generation and duty-cycle adjustability |
| url | http://psasir.upm.edu.my/id/eprint/55852/ http://psasir.upm.edu.my/id/eprint/55852/ http://psasir.upm.edu.my/id/eprint/55852/1/15-JTS%28S%29-0129-2016-4thProof.pdf |