Low power pipelined FFT processor architecture on FPGA
Fast Fourier Transform (FFT) processor is the hardware implementation for FFT algorithms for Discrete Fourier Transform (DFT) which compute any signal in time domain to frequency domain. This processor plays an important role in many applications such as digital video broadcasting, wireless sensor n...
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| Format: | Conference or Workshop Item |
| Language: | English |
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IEEE
2018
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| Online Access: | http://psasir.upm.edu.my/id/eprint/36555/ http://psasir.upm.edu.my/id/eprint/36555/1/Low%20power%20pipelined%20FFT%20processor%20architecture%20on%20FPGA.pdf |
| _version_ | 1848848365464322048 |
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| author | Mohd Hassan, Siti Lailatul Sulaiman, Nasri Abdul Halim, Ili Shairah |
| author_facet | Mohd Hassan, Siti Lailatul Sulaiman, Nasri Abdul Halim, Ili Shairah |
| author_sort | Mohd Hassan, Siti Lailatul |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | Fast Fourier Transform (FFT) processor is the hardware implementation for FFT algorithms for Discrete Fourier Transform (DFT) which compute any signal in time domain to frequency domain. This processor plays an important role in many applications such as digital video broadcasting, wireless sensor network and many more digital signal processing applications, which requires a small area and low power processor. Pipelined FFT processor design on FPGA will speed up the design process and flexibility. This paper provides a survey of three types of pipelined FFT architecture, radix-8, radix-4 single path feedback (R4SDF) and radix-4 single-pasth delay commutator implemented on FPGA. The simulation part is done via Modelsim and verification through Matlab. While the implementation is done via Quartus on the Altera Cyclone IV FPGA board. The performance of these FFT processor is studied. The result shows that radix-8 pipelined FFT have higher power dissipation compared to R4SDF and R4SDC, however R4SDC design has low area design compared to the rest. Overall, all pipelined FFT processor designs are functioning accordingly. |
| first_indexed | 2025-11-15T09:33:21Z |
| format | Conference or Workshop Item |
| id | upm-36555 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T09:33:21Z |
| publishDate | 2018 |
| publisher | IEEE |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-365552020-06-16T01:31:46Z http://psasir.upm.edu.my/id/eprint/36555/ Low power pipelined FFT processor architecture on FPGA Mohd Hassan, Siti Lailatul Sulaiman, Nasri Abdul Halim, Ili Shairah Fast Fourier Transform (FFT) processor is the hardware implementation for FFT algorithms for Discrete Fourier Transform (DFT) which compute any signal in time domain to frequency domain. This processor plays an important role in many applications such as digital video broadcasting, wireless sensor network and many more digital signal processing applications, which requires a small area and low power processor. Pipelined FFT processor design on FPGA will speed up the design process and flexibility. This paper provides a survey of three types of pipelined FFT architecture, radix-8, radix-4 single path feedback (R4SDF) and radix-4 single-pasth delay commutator implemented on FPGA. The simulation part is done via Modelsim and verification through Matlab. While the implementation is done via Quartus on the Altera Cyclone IV FPGA board. The performance of these FFT processor is studied. The result shows that radix-8 pipelined FFT have higher power dissipation compared to R4SDF and R4SDC, however R4SDC design has low area design compared to the rest. Overall, all pipelined FFT processor designs are functioning accordingly. IEEE 2018 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/36555/1/Low%20power%20pipelined%20FFT%20processor%20architecture%20on%20FPGA.pdf Mohd Hassan, Siti Lailatul and Sulaiman, Nasri and Abdul Halim, Ili Shairah (2018) Low power pipelined FFT processor architecture on FPGA. In: 2018 9th IEEE Control and System Graduate Research Colloquium (ICSGRC 2018), 3-4 Aug. 2018, Grand Blue Wave Hotel, Shah Alam, Selangor. (pp. 31-34). 10.1109/ICSGRC.2018.8657583 |
| spellingShingle | Mohd Hassan, Siti Lailatul Sulaiman, Nasri Abdul Halim, Ili Shairah Low power pipelined FFT processor architecture on FPGA |
| title | Low power pipelined FFT processor architecture on FPGA |
| title_full | Low power pipelined FFT processor architecture on FPGA |
| title_fullStr | Low power pipelined FFT processor architecture on FPGA |
| title_full_unstemmed | Low power pipelined FFT processor architecture on FPGA |
| title_short | Low power pipelined FFT processor architecture on FPGA |
| title_sort | low power pipelined fft processor architecture on fpga |
| url | http://psasir.upm.edu.my/id/eprint/36555/ http://psasir.upm.edu.my/id/eprint/36555/ http://psasir.upm.edu.my/id/eprint/36555/1/Low%20power%20pipelined%20FFT%20processor%20architecture%20on%20FPGA.pdf |