Analysis and modeling of ASIC area at early-stage design for standard cell library selection
Area-delay curve is an effective technique to compare and select the appropriate library at different target delay constraint. However, generating area-delay curve requires time-consuming synthesis processes. This paper presents a fast area estimation model to allow the designer to select the optima...
| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2019
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| Online Access: | http://psasir.upm.edu.my/id/eprint/36345/ http://psasir.upm.edu.my/id/eprint/36345/1/Analysis%20and%20modeling%20of%20ASIC%20area%20at%20early-stage%20design%20for%20standard%20cell%20library%20selection.pdf |
| _version_ | 1848848306220826624 |
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| author | Lim, Yang Wei Hashim, Shaiful Jahari Kamsani, Noor 'Ain Mohd Sidek, Roslina Rokhani, Fakhrul Zaman |
| author_facet | Lim, Yang Wei Hashim, Shaiful Jahari Kamsani, Noor 'Ain Mohd Sidek, Roslina Rokhani, Fakhrul Zaman |
| author_sort | Lim, Yang Wei |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | Area-delay curve is an effective technique to compare and select the appropriate library at different target delay constraint. However, generating area-delay curve requires time-consuming synthesis processes. This paper presents a fast area estimation model to allow the designer to select the optimal library for designing area-optimized circuit. The model predicts the area-delay curves for a target circuit based on reduced number of synthesis performed at different frequencies. As compared to the general linear search method, the proposed model with 5 synthesis points results 16.5X-18.6X runtime reduction with average error of 2.74%~5.74% in different height libraries implementation. This shows that the proposed model is beneficial for area optimal library selection at the early stage of design. |
| first_indexed | 2025-11-15T09:32:24Z |
| format | Conference or Workshop Item |
| id | upm-36345 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T09:32:24Z |
| publishDate | 2019 |
| publisher | IEEE |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-363452020-06-15T07:48:40Z http://psasir.upm.edu.my/id/eprint/36345/ Analysis and modeling of ASIC area at early-stage design for standard cell library selection Lim, Yang Wei Hashim, Shaiful Jahari Kamsani, Noor 'Ain Mohd Sidek, Roslina Rokhani, Fakhrul Zaman Area-delay curve is an effective technique to compare and select the appropriate library at different target delay constraint. However, generating area-delay curve requires time-consuming synthesis processes. This paper presents a fast area estimation model to allow the designer to select the optimal library for designing area-optimized circuit. The model predicts the area-delay curves for a target circuit based on reduced number of synthesis performed at different frequencies. As compared to the general linear search method, the proposed model with 5 synthesis points results 16.5X-18.6X runtime reduction with average error of 2.74%~5.74% in different height libraries implementation. This shows that the proposed model is beneficial for area optimal library selection at the early stage of design. IEEE 2019 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/36345/1/Analysis%20and%20modeling%20of%20ASIC%20area%20at%20early-stage%20design%20for%20standard%20cell%20library%20selection.pdf Lim, Yang Wei and Hashim, Shaiful Jahari and Kamsani, Noor 'Ain and Mohd Sidek, Roslina and Rokhani, Fakhrul Zaman (2019) Analysis and modeling of ASIC area at early-stage design for standard cell library selection. In: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 26-29 May 2019, Sapporo, Japan. . 10.1109/ISCAS.2019.8702691 |
| spellingShingle | Lim, Yang Wei Hashim, Shaiful Jahari Kamsani, Noor 'Ain Mohd Sidek, Roslina Rokhani, Fakhrul Zaman Analysis and modeling of ASIC area at early-stage design for standard cell library selection |
| title | Analysis and modeling of ASIC area at early-stage design for standard cell library selection |
| title_full | Analysis and modeling of ASIC area at early-stage design for standard cell library selection |
| title_fullStr | Analysis and modeling of ASIC area at early-stage design for standard cell library selection |
| title_full_unstemmed | Analysis and modeling of ASIC area at early-stage design for standard cell library selection |
| title_short | Analysis and modeling of ASIC area at early-stage design for standard cell library selection |
| title_sort | analysis and modeling of asic area at early-stage design for standard cell library selection |
| url | http://psasir.upm.edu.my/id/eprint/36345/ http://psasir.upm.edu.my/id/eprint/36345/ http://psasir.upm.edu.my/id/eprint/36345/1/Analysis%20and%20modeling%20of%20ASIC%20area%20at%20early-stage%20design%20for%20standard%20cell%20library%20selection.pdf |