Fabrication and simulation of lithographically defined junctionless lateral gate silicon nanowire transistors - Larki, Farhad (2012)
Nowadays most of the industrial technology in fabrication of transistors is based on the use of semiconductor junctions. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms in the semiconductor, the formation of ultra-shallow junctions with high doping concentration gradients has become an increasingly difficult challenge for the semiconductor industry. Thus, scaling-down of semiconductor devices, which remarkably follows Moore's law during the last 40 years, has pushed complementary metal–oxide–semiconductor (CMOS) devices close to fundamental limits. In order to keep the validity of Moore's law, device down scaling is not enough. So called material and geometry technology boosters have been introduced. High-k dielectrics, silicon-on-insulator substrates or strained silicon are some booster examples that were used at sub-micron scale.