Dual sampling sigma delta analog to digital converter
An analog to digital converter (ADC) (100), includes, a sigma delta modulator (102) including a modulator input configured for receiving an analog input signal (104), and a modulator output configured for providing multiple digital signals (105, 107). The ADC further includes a clock (106) operating...
| Main Authors: | , , |
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| Format: | Patent |
| Published: |
2012
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| Online Access: | http://psasir.upm.edu.my/id/eprint/33572/ |
| _version_ | 1848847535470280704 |
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| author | Mohd Isa, Maryam Noor Shah, Mohd Syahril Hamidon, Mohd Nizar |
| author_facet | Mohd Isa, Maryam Noor Shah, Mohd Syahril Hamidon, Mohd Nizar |
| author_sort | Mohd Isa, Maryam |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | An analog to digital converter (ADC) (100), includes, a sigma delta modulator (102) including a modulator input configured for receiving an analog input signal (104), and a modulator output configured for providing multiple digital signals (105, 107). The ADC further includes a clock (106) operating at a conversion clock frequency for producing a clock signal (108), and a decimator (110) for processing the multiple digital signals produced by the sigma delta modulator (102) and generating an output digital signal (150), and the decimator (110) includes multiple decimation elements (112, 114) and a combining element (116) for generating the output digital signal (150) with N-bits. The sigma delta modulator (102) further includes a comparator (118) having a first input (120) for receiving the analog input signal (104), a second input (121) for receiving an analog estimate of the analog input signal (104), and a comparator output (122). |
| first_indexed | 2025-11-15T09:20:09Z |
| format | Patent |
| id | upm-33572 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| last_indexed | 2025-11-15T09:20:09Z |
| publishDate | 2012 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-335722016-01-19T02:09:43Z http://psasir.upm.edu.my/id/eprint/33572/ Dual sampling sigma delta analog to digital converter Mohd Isa, Maryam Noor Shah, Mohd Syahril Hamidon, Mohd Nizar An analog to digital converter (ADC) (100), includes, a sigma delta modulator (102) including a modulator input configured for receiving an analog input signal (104), and a modulator output configured for providing multiple digital signals (105, 107). The ADC further includes a clock (106) operating at a conversion clock frequency for producing a clock signal (108), and a decimator (110) for processing the multiple digital signals produced by the sigma delta modulator (102) and generating an output digital signal (150), and the decimator (110) includes multiple decimation elements (112, 114) and a combining element (116) for generating the output digital signal (150) with N-bits. The sigma delta modulator (102) further includes a comparator (118) having a first input (120) for receiving the analog input signal (104), a second input (121) for receiving an analog estimate of the analog input signal (104), and a comparator output (122). 2012-11-06 Patent NonPeerReviewed Maryam Mohd Isa (2012) Dual sampling sigma delta analog to digital converter. PI2012700893. |
| spellingShingle | Mohd Isa, Maryam Noor Shah, Mohd Syahril Hamidon, Mohd Nizar Dual sampling sigma delta analog to digital converter |
| title | Dual sampling sigma delta analog to digital converter |
| title_full | Dual sampling sigma delta analog to digital converter |
| title_fullStr | Dual sampling sigma delta analog to digital converter |
| title_full_unstemmed | Dual sampling sigma delta analog to digital converter |
| title_short | Dual sampling sigma delta analog to digital converter |
| title_sort | dual sampling sigma delta analog to digital converter |
| url | http://psasir.upm.edu.my/id/eprint/33572/ |