Pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography
The spark of aggressive scaling of transistors was started after the Moors law on prediction of device dimensions. Recently, among the several types of transistors, junctionless transistors were considered as one of the promising alternative for new generation of nanotransistors. In this work, we in...
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| Format: | Article |
| Language: | English |
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Trans Tech Publications
2013
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| Online Access: | http://psasir.upm.edu.my/id/eprint/30403/ http://psasir.upm.edu.my/id/eprint/30403/1/Pinch.pdf |
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| author | Larki, Farhad Dehzangi, Arash Hassan, Jumiah Abedini, Alam Saion, Elias Hutagalung, Sabar D. Abdullah, A. Makarimi Hamidon, Mohd. Nizar |
| author_facet | Larki, Farhad Dehzangi, Arash Hassan, Jumiah Abedini, Alam Saion, Elias Hutagalung, Sabar D. Abdullah, A. Makarimi Hamidon, Mohd. Nizar |
| author_sort | Larki, Farhad |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | The spark of aggressive scaling of transistors was started after the Moors law on prediction of device dimensions. Recently, among the several types of transistors, junctionless transistors were considered as one of the promising alternative for new generation of nanotransistors. In this work, we investigate the pinch-off effect in double gate and single gate junctionless lateral gate transistors. The transistors are fabricated on lightly doped (1015) p-type Silicon-on-insulator wafer by using an atomic force microscopy nanolithography technique. The transistors are normally on state devices and working in depletion mode. The behavior of the devices confirms the normal behavior of the junctionless transistors. The pinch-off effect appears at VG +2.0 V and VG +2.5 V for fabricated double gate and single structure, respectively. On state current is in the order of 10-9 (A) for both structures due to low doping concentration. The single gate and double gate devices exhibit an Ion/Ioff of approximately 105 and 106, respectively. |
| first_indexed | 2025-11-15T09:06:20Z |
| format | Article |
| id | upm-30403 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T09:06:20Z |
| publishDate | 2013 |
| publisher | Trans Tech Publications |
| recordtype | eprints |
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| spelling | upm-304032015-10-01T08:26:43Z http://psasir.upm.edu.my/id/eprint/30403/ Pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography Larki, Farhad Dehzangi, Arash Hassan, Jumiah Abedini, Alam Saion, Elias Hutagalung, Sabar D. Abdullah, A. Makarimi Hamidon, Mohd. Nizar The spark of aggressive scaling of transistors was started after the Moors law on prediction of device dimensions. Recently, among the several types of transistors, junctionless transistors were considered as one of the promising alternative for new generation of nanotransistors. In this work, we investigate the pinch-off effect in double gate and single gate junctionless lateral gate transistors. The transistors are fabricated on lightly doped (1015) p-type Silicon-on-insulator wafer by using an atomic force microscopy nanolithography technique. The transistors are normally on state devices and working in depletion mode. The behavior of the devices confirms the normal behavior of the junctionless transistors. The pinch-off effect appears at VG +2.0 V and VG +2.5 V for fabricated double gate and single structure, respectively. On state current is in the order of 10-9 (A) for both structures due to low doping concentration. The single gate and double gate devices exhibit an Ion/Ioff of approximately 105 and 106, respectively. Trans Tech Publications 2013 Article PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/30403/1/Pinch.pdf Larki, Farhad and Dehzangi, Arash and Hassan, Jumiah and Abedini, Alam and Saion, Elias and Hutagalung, Sabar D. and Abdullah, A. Makarimi and Hamidon, Mohd. Nizar (2013) Pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography. Nano Hybrids, 4. pp. 33-45. ISSN 2235-8129; ESSN: 2234-9871 10.4028/www.scientific.net/NH.4.33 |
| spellingShingle | Larki, Farhad Dehzangi, Arash Hassan, Jumiah Abedini, Alam Saion, Elias Hutagalung, Sabar D. Abdullah, A. Makarimi Hamidon, Mohd. Nizar Pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography |
| title | Pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography |
| title_full | Pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography |
| title_fullStr | Pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography |
| title_full_unstemmed | Pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography |
| title_short | Pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography |
| title_sort | pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography |
| url | http://psasir.upm.edu.my/id/eprint/30403/ http://psasir.upm.edu.my/id/eprint/30403/ http://psasir.upm.edu.my/id/eprint/30403/1/Pinch.pdf |