Study the characteristic of p-type junction-less side gate silicon nanowire transistor fabricated by atomic force microscopy lithography
Problem statement: Nanotransistor now is one of the most promising fields in nanoelectronic in order to less energy consuming and application to create developed programmable information processors. Most of Computing and communications companies invest hundreds of millions of dollars in research fun...
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| Format: | Article |
| Language: | English |
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Science Publications
2011
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| Online Access: | http://psasir.upm.edu.my/id/eprint/25031/ http://psasir.upm.edu.my/id/eprint/25031/1/ajassp.2011.872.877.pdf |
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| author | Dehzangi, Arash Larki, Farhad Saion, Elias Hatagalung, Sabar D. Abdullah, Ahmad Makarimi Hamidon, Mohd Nizar Hassan, Jumiah |
| author_facet | Dehzangi, Arash Larki, Farhad Saion, Elias Hatagalung, Sabar D. Abdullah, Ahmad Makarimi Hamidon, Mohd Nizar Hassan, Jumiah |
| author_sort | Dehzangi, Arash |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | Problem statement: Nanotransistor now is one of the most promising fields in nanoelectronic in order to less energy consuming and application to create developed programmable information processors. Most of Computing and communications companies invest hundreds of millions of dollars in research funds every year to develop smaller transistors. Approach: The Junction-less side gate silicon Nano-wire transistor has been fabricated by Atomic Force Microscopy (AFM) and wet etching on p-type Silicon On Insulator (SOI) wafer. Then, we checked the characteristic and conductance trend in this device regarding to semi-classical approach by Semiconductor Probe Analyser (SPA). Results: We observe in characteristic of the device directly proportionality of the negative gate voltage and Source-Drain current. In semi classical approach, negative Gate voltage falling down the energy States of the Nano-wire between the source and the drain. The graph for positive gate voltage plotted as well to check. In other hand, the conductance will be following characteristic due to varying the gate voltage under the different drain-source voltage. Conclusion: The channel energy states are supposed to locate between two electrochemical potentials of the contacts in order to transform the charge. For the p-type channel the transform of the carriers is located in valence band and changing the positive or negative gate voltage, make the valence band energy states out of or in the area between the electrochemical potentials of the contacts causing the current reduced or increased. |
| first_indexed | 2025-11-15T08:43:00Z |
| format | Article |
| id | upm-25031 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T08:43:00Z |
| publishDate | 2011 |
| publisher | Science Publications |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-250312017-11-23T09:51:13Z http://psasir.upm.edu.my/id/eprint/25031/ Study the characteristic of p-type junction-less side gate silicon nanowire transistor fabricated by atomic force microscopy lithography Dehzangi, Arash Larki, Farhad Saion, Elias Hatagalung, Sabar D. Abdullah, Ahmad Makarimi Hamidon, Mohd Nizar Hassan, Jumiah Problem statement: Nanotransistor now is one of the most promising fields in nanoelectronic in order to less energy consuming and application to create developed programmable information processors. Most of Computing and communications companies invest hundreds of millions of dollars in research funds every year to develop smaller transistors. Approach: The Junction-less side gate silicon Nano-wire transistor has been fabricated by Atomic Force Microscopy (AFM) and wet etching on p-type Silicon On Insulator (SOI) wafer. Then, we checked the characteristic and conductance trend in this device regarding to semi-classical approach by Semiconductor Probe Analyser (SPA). Results: We observe in characteristic of the device directly proportionality of the negative gate voltage and Source-Drain current. In semi classical approach, negative Gate voltage falling down the energy States of the Nano-wire between the source and the drain. The graph for positive gate voltage plotted as well to check. In other hand, the conductance will be following characteristic due to varying the gate voltage under the different drain-source voltage. Conclusion: The channel energy states are supposed to locate between two electrochemical potentials of the contacts in order to transform the charge. For the p-type channel the transform of the carriers is located in valence band and changing the positive or negative gate voltage, make the valence band energy states out of or in the area between the electrochemical potentials of the contacts causing the current reduced or increased. Science Publications 2011 Article PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/25031/1/ajassp.2011.872.877.pdf Dehzangi, Arash and Larki, Farhad and Saion, Elias and Hatagalung, Sabar D. and Abdullah, Ahmad Makarimi and Hamidon, Mohd Nizar and Hassan, Jumiah (2011) Study the characteristic of p-type junction-less side gate silicon nanowire transistor fabricated by atomic force microscopy lithography. American Journal of Applied Sciences, 8 (9). pp. 872-877. ISSN 1546-9239; ESSN: 1554-3641 http://thescipub.com/abstract/10.3844/ajassp.2011.872.877 10.3844/ajassp.2011.872.877 |
| spellingShingle | Dehzangi, Arash Larki, Farhad Saion, Elias Hatagalung, Sabar D. Abdullah, Ahmad Makarimi Hamidon, Mohd Nizar Hassan, Jumiah Study the characteristic of p-type junction-less side gate silicon nanowire transistor fabricated by atomic force microscopy lithography |
| title | Study the characteristic of p-type junction-less side gate silicon nanowire transistor fabricated by atomic force microscopy lithography |
| title_full | Study the characteristic of p-type junction-less side gate silicon nanowire transistor fabricated by atomic force microscopy lithography |
| title_fullStr | Study the characteristic of p-type junction-less side gate silicon nanowire transistor fabricated by atomic force microscopy lithography |
| title_full_unstemmed | Study the characteristic of p-type junction-less side gate silicon nanowire transistor fabricated by atomic force microscopy lithography |
| title_short | Study the characteristic of p-type junction-less side gate silicon nanowire transistor fabricated by atomic force microscopy lithography |
| title_sort | study the characteristic of p-type junction-less side gate silicon nanowire transistor fabricated by atomic force microscopy lithography |
| url | http://psasir.upm.edu.my/id/eprint/25031/ http://psasir.upm.edu.my/id/eprint/25031/ http://psasir.upm.edu.my/id/eprint/25031/ http://psasir.upm.edu.my/id/eprint/25031/1/ajassp.2011.872.877.pdf |