Electrical performance of 0.5 µm MOSFET on bond-and-etch-back silicon-on-insulator(BESOI) substrate
0.5 µm gate length MOSFET is fabricated on Bond-and-Etch-Back Silicon-On-Insulator (BESOI) substrate using bulk CMOS technology. For the purpose of silicon layer thickness adjustment, sacrificial oxidation is implemented on the device layer of 1.5 ± 0.5 µm device layer and 2 µm buried oxide thicknes...
| Main Authors: | , , , |
|---|---|
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2002
|
| Online Access: | http://psasir.upm.edu.my/id/eprint/18493/ http://psasir.upm.edu.my/id/eprint/18493/1/18493.pdf |
| _version_ | 1848843523843948544 |
|---|---|
| author | Abdullah, Wan Fazlida Hanim Mohd Sidek, Roslina Mohd Saari, Shahrul Aman Ahmad, Mohd Rais |
| author_facet | Abdullah, Wan Fazlida Hanim Mohd Sidek, Roslina Mohd Saari, Shahrul Aman Ahmad, Mohd Rais |
| author_sort | Abdullah, Wan Fazlida Hanim |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | 0.5 µm gate length MOSFET is fabricated on Bond-and-Etch-Back Silicon-On-Insulator (BESOI) substrate using bulk CMOS technology. For the purpose of silicon layer thickness adjustment, sacrificial oxidation is implemented on the device layer of 1.5 ± 0.5 µm device layer and 2 µm buried oxide thickness. Effects of the BESOI substrate and prior sacrificial oxidation on the threshold voltage, drive current and off-state leakage current are investigated from preliminary electrical measurements. Comparison between devices fabricated on bulk silicon and BESOI substrate were carried out. Results are presented in intrinsic transistor performance plots illustrating the relation and variation of critical parameters over the entire wafer. |
| first_indexed | 2025-11-15T08:16:23Z |
| format | Conference or Workshop Item |
| id | upm-18493 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T08:16:23Z |
| publishDate | 2002 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-184932015-02-26T04:24:00Z http://psasir.upm.edu.my/id/eprint/18493/ Electrical performance of 0.5 µm MOSFET on bond-and-etch-back silicon-on-insulator(BESOI) substrate Abdullah, Wan Fazlida Hanim Mohd Sidek, Roslina Mohd Saari, Shahrul Aman Ahmad, Mohd Rais 0.5 µm gate length MOSFET is fabricated on Bond-and-Etch-Back Silicon-On-Insulator (BESOI) substrate using bulk CMOS technology. For the purpose of silicon layer thickness adjustment, sacrificial oxidation is implemented on the device layer of 1.5 ± 0.5 µm device layer and 2 µm buried oxide thickness. Effects of the BESOI substrate and prior sacrificial oxidation on the threshold voltage, drive current and off-state leakage current are investigated from preliminary electrical measurements. Comparison between devices fabricated on bulk silicon and BESOI substrate were carried out. Results are presented in intrinsic transistor performance plots illustrating the relation and variation of critical parameters over the entire wafer. 2002 Conference or Workshop Item NonPeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/18493/1/18493.pdf Abdullah, Wan Fazlida Hanim and Mohd Sidek, Roslina and Mohd Saari, Shahrul Aman and Ahmad, Mohd Rais (2002) Electrical performance of 0.5 µm MOSFET on bond-and-etch-back silicon-on-insulator(BESOI) substrate. In: 2nd World Engineering Congress, 22 - 25 July 2002, Sarawak, Malaysia. (pp. 187-192). |
| spellingShingle | Abdullah, Wan Fazlida Hanim Mohd Sidek, Roslina Mohd Saari, Shahrul Aman Ahmad, Mohd Rais Electrical performance of 0.5 µm MOSFET on bond-and-etch-back silicon-on-insulator(BESOI) substrate |
| title | Electrical performance of 0.5 µm MOSFET on bond-and-etch-back silicon-on-insulator(BESOI) substrate |
| title_full | Electrical performance of 0.5 µm MOSFET on bond-and-etch-back silicon-on-insulator(BESOI) substrate |
| title_fullStr | Electrical performance of 0.5 µm MOSFET on bond-and-etch-back silicon-on-insulator(BESOI) substrate |
| title_full_unstemmed | Electrical performance of 0.5 µm MOSFET on bond-and-etch-back silicon-on-insulator(BESOI) substrate |
| title_short | Electrical performance of 0.5 µm MOSFET on bond-and-etch-back silicon-on-insulator(BESOI) substrate |
| title_sort | electrical performance of 0.5 µm mosfet on bond-and-etch-back silicon-on-insulator(besoi) substrate |
| url | http://psasir.upm.edu.my/id/eprint/18493/ http://psasir.upm.edu.my/id/eprint/18493/1/18493.pdf |