Development of high speed booth multiplier with optimized stuck-at fault implementation
Multiplier is a basic device in many digital systems such as signal processor, calculator and micro controller. Thus a fast multiplier is very important in improving the speed of the digital system. In general, there are two basic approaches to enhance the speed of the multiplier, Booth Algorithm...
| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
Universiti Putra Malaysia Press
2002
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| Online Access: | http://psasir.upm.edu.my/id/eprint/18396/ http://psasir.upm.edu.my/id/eprint/18396/1/18396.pdf |
| _version_ | 1848843498698047488 |
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| author | Mohammed Khalid, Muhammad Nazir Wan Hasan, Wan Zuha Sulaiman, Nasri Wagiran, Rahman |
| author_facet | Mohammed Khalid, Muhammad Nazir Wan Hasan, Wan Zuha Sulaiman, Nasri Wagiran, Rahman |
| author_sort | Mohammed Khalid, Muhammad Nazir |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | Multiplier is a basic device in many digital systems such as signal processor, calculator and micro controller.
Thus a fast multiplier is very important in improving the speed of the digital system. In general, there are two basic
approaches to enhance the speed of the multiplier, Booth Algorithm and the Wallace Tree compressors or counter. Booth
Multiplier is proposed due to make sure that multiplication of positive and negative values can be done in 2's complement system operation. For that reason, Booth Multiplier is very demanding to many microprocessor or micro controller chip manufacturers. A part from that, time to market elcaupare very consuming to them, thus failure design can increase production operation and also total costing. So applied DFT is needed due to reduce the production time and total costing. Deterministic technique will be used to detect failure circuit base on test pattern generation. The Test Pattern Generation(TPG) is the process of providing a set of test stimuli plus expected fault free response to meet the requirement of a target fault list. Test for logic circuits are generated to set a sensitive path for a specific fault-effect such Stuck-at-Fault model. |
| first_indexed | 2025-11-15T08:15:59Z |
| format | Conference or Workshop Item |
| id | upm-18396 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T08:15:59Z |
| publishDate | 2002 |
| publisher | Universiti Putra Malaysia Press |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-183962015-02-27T02:48:19Z http://psasir.upm.edu.my/id/eprint/18396/ Development of high speed booth multiplier with optimized stuck-at fault implementation Mohammed Khalid, Muhammad Nazir Wan Hasan, Wan Zuha Sulaiman, Nasri Wagiran, Rahman Multiplier is a basic device in many digital systems such as signal processor, calculator and micro controller. Thus a fast multiplier is very important in improving the speed of the digital system. In general, there are two basic approaches to enhance the speed of the multiplier, Booth Algorithm and the Wallace Tree compressors or counter. Booth Multiplier is proposed due to make sure that multiplication of positive and negative values can be done in 2's complement system operation. For that reason, Booth Multiplier is very demanding to many microprocessor or micro controller chip manufacturers. A part from that, time to market elcaupare very consuming to them, thus failure design can increase production operation and also total costing. So applied DFT is needed due to reduce the production time and total costing. Deterministic technique will be used to detect failure circuit base on test pattern generation. The Test Pattern Generation(TPG) is the process of providing a set of test stimuli plus expected fault free response to meet the requirement of a target fault list. Test for logic circuits are generated to set a sensitive path for a specific fault-effect such Stuck-at-Fault model. Universiti Putra Malaysia Press 2002 Conference or Workshop Item NonPeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/18396/1/18396.pdf Mohammed Khalid, Muhammad Nazir and Wan Hasan, Wan Zuha and Sulaiman, Nasri and Wagiran, Rahman (2002) Development of high speed booth multiplier with optimized stuck-at fault implementation. In: 2nd World Engineering Congress, 22 - 25 July 2002, Sarawak, Malaysia. (pp. 193-198). |
| spellingShingle | Mohammed Khalid, Muhammad Nazir Wan Hasan, Wan Zuha Sulaiman, Nasri Wagiran, Rahman Development of high speed booth multiplier with optimized stuck-at fault implementation |
| title | Development of high speed booth multiplier with optimized
stuck-at fault implementation |
| title_full | Development of high speed booth multiplier with optimized
stuck-at fault implementation |
| title_fullStr | Development of high speed booth multiplier with optimized
stuck-at fault implementation |
| title_full_unstemmed | Development of high speed booth multiplier with optimized
stuck-at fault implementation |
| title_short | Development of high speed booth multiplier with optimized
stuck-at fault implementation |
| title_sort | development of high speed booth multiplier with optimized
stuck-at fault implementation |
| url | http://psasir.upm.edu.my/id/eprint/18396/ http://psasir.upm.edu.my/id/eprint/18396/1/18396.pdf |