Optimising built-in-self-test using K-map LFSR on parallel multiplier circuit
Current trend in Integrated Circuits (IC) implementation such as System-on-Chip (SOC) has contributed significant advantages in electronic product features such as high circuit performance with high number of functions, small physical area and high reliability. Therefore, including Built-In-Self-Te...
| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2002
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| Online Access: | http://psasir.upm.edu.my/id/eprint/18394/ http://psasir.upm.edu.my/id/eprint/18394/1/18394.pdf |
| _version_ | 1848843498196828160 |
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| author | Wan Hasan, Wan Zuha Ali, Mohd Liakot Romli, Norfazliana |
| author_facet | Wan Hasan, Wan Zuha Ali, Mohd Liakot Romli, Norfazliana |
| author_sort | Wan Hasan, Wan Zuha |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | Current trend in Integrated Circuits (IC) implementation such as System-on-Chip (SOC) has contributed significant advantages in electronic product features such as high circuit performance with high number of functions,
small physical area and high reliability. Therefore, including Built-In-Self-Test (BIST) facility into each subsystem of SOC is considered a good solution. Commonly, BIST structure is based on random test data generation from a Linear Feedback Shift Register (LFSR) due to its simple, small and economical circuit structure. For this reason, development of test pattern" for BIST based on combination of K-map LFSR and deterministic approach could provide one of the solutions to reduce the testing time. This paper describes the test efficiencies based on combination of K-map LFSR features and deterministic test pattern. A parallel multiplier that considered as one of the demanding subsystems is chosen to verify the proposed BIST performance. |
| first_indexed | 2025-11-15T08:15:59Z |
| format | Conference or Workshop Item |
| id | upm-18394 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T08:15:59Z |
| publishDate | 2002 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-183942020-05-14T01:48:56Z http://psasir.upm.edu.my/id/eprint/18394/ Optimising built-in-self-test using K-map LFSR on parallel multiplier circuit Wan Hasan, Wan Zuha Ali, Mohd Liakot Romli, Norfazliana Current trend in Integrated Circuits (IC) implementation such as System-on-Chip (SOC) has contributed significant advantages in electronic product features such as high circuit performance with high number of functions, small physical area and high reliability. Therefore, including Built-In-Self-Test (BIST) facility into each subsystem of SOC is considered a good solution. Commonly, BIST structure is based on random test data generation from a Linear Feedback Shift Register (LFSR) due to its simple, small and economical circuit structure. For this reason, development of test pattern" for BIST based on combination of K-map LFSR and deterministic approach could provide one of the solutions to reduce the testing time. This paper describes the test efficiencies based on combination of K-map LFSR features and deterministic test pattern. A parallel multiplier that considered as one of the demanding subsystems is chosen to verify the proposed BIST performance. 2002 Conference or Workshop Item NonPeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/18394/1/18394.pdf Wan Hasan, Wan Zuha and Ali, Mohd Liakot and Romli, Norfazliana (2002) Optimising built-in-self-test using K-map LFSR on parallel multiplier circuit. In: 2nd World Engineering Congress, 22-25 July 2002, Sarawak, Malaysia. (pp. 233-237). |
| spellingShingle | Wan Hasan, Wan Zuha Ali, Mohd Liakot Romli, Norfazliana Optimising built-in-self-test using K-map LFSR on parallel multiplier circuit |
| title | Optimising built-in-self-test using K-map LFSR on parallel multiplier circuit |
| title_full | Optimising built-in-self-test using K-map LFSR on parallel multiplier circuit |
| title_fullStr | Optimising built-in-self-test using K-map LFSR on parallel multiplier circuit |
| title_full_unstemmed | Optimising built-in-self-test using K-map LFSR on parallel multiplier circuit |
| title_short | Optimising built-in-self-test using K-map LFSR on parallel multiplier circuit |
| title_sort | optimising built-in-self-test using k-map lfsr on parallel multiplier circuit |
| url | http://psasir.upm.edu.my/id/eprint/18394/ http://psasir.upm.edu.my/id/eprint/18394/1/18394.pdf |