A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI

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A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI

Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to n...

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Bibliographic Details
Main Authors:	Ji, Yuxin, Zhang, Yuhang, Chen, Changyan, Zhao, Jian, Rokhani, Fakhrul Zaman, Ismail, Yehea, Li, Yongfu
Format:	Article
Published:	Institute of Electrical and Electronics Engineers 2024
Online Access:	http://psasir.upm.edu.my/id/eprint/114238/

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