A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI
Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to n...
| Main Authors: | , , , , , , |
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| Format: | Article |
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Institute of Electrical and Electronics Engineers
2024
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| Online Access: | http://psasir.upm.edu.my/id/eprint/114238/ |
| _version_ | 1848866434781806592 |
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| author | Ji, Yuxin Zhang, Yuhang Chen, Changyan Zhao, Jian Rokhani, Fakhrul Zaman Ismail, Yehea Li, Yongfu |
| author_facet | Ji, Yuxin Zhang, Yuhang Chen, Changyan Zhao, Jian Rokhani, Fakhrul Zaman Ismail, Yehea Li, Yongfu |
| author_sort | Ji, Yuxin |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW, 1.4 × -3.8 × less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step, 1.2 × -4 × less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs). |
| first_indexed | 2025-11-15T14:20:33Z |
| format | Article |
| id | upm-114238 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| last_indexed | 2025-11-15T14:20:33Z |
| publishDate | 2024 |
| publisher | Institute of Electrical and Electronics Engineers |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-1142382025-01-08T06:21:21Z http://psasir.upm.edu.my/id/eprint/114238/ A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI Ji, Yuxin Zhang, Yuhang Chen, Changyan Zhao, Jian Rokhani, Fakhrul Zaman Ismail, Yehea Li, Yongfu Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW, 1.4 × -3.8 × less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step, 1.2 × -4 × less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs). Institute of Electrical and Electronics Engineers 2024-09-20 Article PeerReviewed Ji, Yuxin and Zhang, Yuhang and Chen, Changyan and Zhao, Jian and Rokhani, Fakhrul Zaman and Ismail, Yehea and Li, Yongfu (2024) A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. pp. 1-5. ISSN 1063-8210; eISSN: 1557-9999 https://ieeexplore.ieee.org/document/10684787/ 10.1109/TVLSI.2024.3453946 |
| spellingShingle | Ji, Yuxin Zhang, Yuhang Chen, Changyan Zhao, Jian Rokhani, Fakhrul Zaman Ismail, Yehea Li, Yongfu A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI |
| title | A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI |
| title_full | A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI |
| title_fullStr | A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI |
| title_full_unstemmed | A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI |
| title_short | A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI |
| title_sort | 0.4 v, 12.2 pw leakage, 36.5 fj/step switching efficiency data retention flip-flop in 22 nm fdsoi |
| url | http://psasir.upm.edu.my/id/eprint/114238/ http://psasir.upm.edu.my/id/eprint/114238/ http://psasir.upm.edu.my/id/eprint/114238/ |