Design of High-Speed Multiplier with Optimised Builtinself-Test
Current trend in Integrated Circuits (IC) implementation such as System-on-Chip has contributed significant advantages in electronic product features such as high circuit performance with high number of functions, small physical area and high reliability. Since the development of System-on-Chip, whi...
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| Format: | Thesis |
| Language: | English English |
| Published: |
2000
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| Online Access: | http://psasir.upm.edu.my/id/eprint/10478/ http://psasir.upm.edu.my/id/eprint/10478/1/FK_2000_14.pdf |
| _version_ | 1848841435656224768 |
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| author | Wan Hasan, Wan Zuha |
| author_facet | Wan Hasan, Wan Zuha |
| author_sort | Wan Hasan, Wan Zuha |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | Current trend in Integrated Circuits (IC) implementation such as System-on-Chip has contributed significant advantages in electronic product features such as high circuit performance with high number of functions, small physical area and high reliability. Since the development of System-on-Chip, which is based on integrating subsystems supplied by various Intellectual Properties (IP) Block vendors, the required design time is shorter when compared to that of full-custom IC implementation. However, testing each internal subsystems using the common scan-path method where test data are generated and analyzed externally is considered too time consuming when the number of subsystems is high. Therefore, by including Built-In-Self-Test (BIST) facility into each subsystem is considered a good solution.
Commonly, BIST structure is based on random test data generation from a Linear Feedback Shift Register (LFSR) due to its simple, small and economical circuit structure. Since t he number of subsystems in an IC chip is going to be increased from time to time, improvement on the BIST approach is required to provide shorter testing time while keeping the good features of LFSR. For this reason, development of test pattern for BIST based on combination of
LFSR and deterministic approach could provide one of the solutions to reduce the testing time. In this research, the possibility of combining LFSR features and deterministic test pattern was carried out. A parallel high-speed multiplier considered as one of the demanding subsystems was chosen to verify the proposed BIST performance. Results show that the testing time (with 100% fault coverage) was
reduced significantly when compared to the testing time taken for the BIST that was totally based on random test data generation. One of the reasons for this achievement is only one basic cell of the multiplier is required to determine the test pattern by considering the data flow from one cell to another. Identical test data can then be applied to both multiplier inputs simultaneously. This is the significant finding of the research. Further works based
on the finding are also identified. |
| first_indexed | 2025-11-15T07:43:12Z |
| format | Thesis |
| id | upm-10478 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English English |
| last_indexed | 2025-11-15T07:43:12Z |
| publishDate | 2000 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-104782024-04-02T00:37:27Z http://psasir.upm.edu.my/id/eprint/10478/ Design of High-Speed Multiplier with Optimised Builtinself-Test Wan Hasan, Wan Zuha Current trend in Integrated Circuits (IC) implementation such as System-on-Chip has contributed significant advantages in electronic product features such as high circuit performance with high number of functions, small physical area and high reliability. Since the development of System-on-Chip, which is based on integrating subsystems supplied by various Intellectual Properties (IP) Block vendors, the required design time is shorter when compared to that of full-custom IC implementation. However, testing each internal subsystems using the common scan-path method where test data are generated and analyzed externally is considered too time consuming when the number of subsystems is high. Therefore, by including Built-In-Self-Test (BIST) facility into each subsystem is considered a good solution. Commonly, BIST structure is based on random test data generation from a Linear Feedback Shift Register (LFSR) due to its simple, small and economical circuit structure. Since t he number of subsystems in an IC chip is going to be increased from time to time, improvement on the BIST approach is required to provide shorter testing time while keeping the good features of LFSR. For this reason, development of test pattern for BIST based on combination of LFSR and deterministic approach could provide one of the solutions to reduce the testing time. In this research, the possibility of combining LFSR features and deterministic test pattern was carried out. A parallel high-speed multiplier considered as one of the demanding subsystems was chosen to verify the proposed BIST performance. Results show that the testing time (with 100% fault coverage) was reduced significantly when compared to the testing time taken for the BIST that was totally based on random test data generation. One of the reasons for this achievement is only one basic cell of the multiplier is required to determine the test pattern by considering the data flow from one cell to another. Identical test data can then be applied to both multiplier inputs simultaneously. This is the significant finding of the research. Further works based on the finding are also identified. 2000-03 Thesis NonPeerReviewed text en http://psasir.upm.edu.my/id/eprint/10478/1/FK_2000_14.pdf Wan Hasan, Wan Zuha (2000) Design of High-Speed Multiplier with Optimised Builtinself-Test. Masters thesis, Universiti Putra Malaysia. Multiplier (Economics) English |
| spellingShingle | Multiplier (Economics) Wan Hasan, Wan Zuha Design of High-Speed Multiplier with Optimised Builtinself-Test |
| title | Design of High-Speed Multiplier with Optimised Builtinself-Test |
| title_full | Design of High-Speed Multiplier with Optimised Builtinself-Test |
| title_fullStr | Design of High-Speed Multiplier with Optimised Builtinself-Test |
| title_full_unstemmed | Design of High-Speed Multiplier with Optimised Builtinself-Test |
| title_short | Design of High-Speed Multiplier with Optimised Builtinself-Test |
| title_sort | design of high-speed multiplier with optimised builtinself-test |
| topic | Multiplier (Economics) |
| url | http://psasir.upm.edu.my/id/eprint/10478/ http://psasir.upm.edu.my/id/eprint/10478/1/FK_2000_14.pdf |