Performance of domino logic with dynamic body biased keeper
Domino logic have become extremely popular in the design of today's high performance processors because they offer fast switching speeds compared to static CMOS circuits. However, scale down the domino logic requires t hreshold voltage reduction and supply voltage s...
| Main Author: | |
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| Format: | Final Year Project Report / IMRAD |
| Language: | English |
| Published: |
Universiti Malaysia Sarawak, UNIMAS
2009
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| Subjects: | |
| Online Access: | http://ir.unimas.my/id/eprint/6537/ http://ir.unimas.my/id/eprint/6537/1/Kiew%20Kwong%20ft.pdf |
| _version_ | 1848835937359888384 |
|---|---|
| author | Kiew,, Kwong Chwen. |
| author_facet | Kiew,, Kwong Chwen. |
| author_sort | Kiew,, Kwong Chwen. |
| building | UNIMAS Institutional Repository |
| collection | Online Access |
| description | Domino logic
have become extremely popular in the design of today's high
performance processors because they offer fast switching speeds
compared to static
CMOS circuits.
However,
scale down the domino logic requires t
hreshold voltage
reduction
and
supply
voltage scaling to maintain the performance, but it increases
the
subthreshold leakage currents
exponentially
. To solve
this problem, keeper
transistor is introduced. Domino logic with
standard
keeper
however
still has
a
proble
m with a contention current. In this project, domino logic with dynamic body
biased keeper technique is proposed
to achieve high performance domino logic in
terms of speed and power dissipation.
The new design is proposed by adding a sleep
transis
tor, reduces the capacitive by half to 1fF and also connects a new resistor,
R
a
in series with the load resistor,
R
L
. The proposed design of domino logic with
dynamic body biased keeper shows improvement of average 37.60% in terms of
speed, 67.89% in terms
of power dissipation and 80.00% in terms of power delay
product when compared to domino logic with standard keeper. Meanwhile, the
design also manage to enhance speed by 26.72%, reduce power by 67.81% and
reduce power delay product by 76.44 % comparing to
previous DBBK circuit. |
| first_indexed | 2025-11-15T06:15:48Z |
| format | Final Year Project Report / IMRAD |
| id | unimas-6537 |
| institution | Universiti Malaysia Sarawak |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T06:15:48Z |
| publishDate | 2009 |
| publisher | Universiti Malaysia Sarawak, UNIMAS |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | unimas-65372023-10-06T09:07:33Z http://ir.unimas.my/id/eprint/6537/ Performance of domino logic with dynamic body biased keeper Kiew,, Kwong Chwen. TK Electrical engineering. Electronics Nuclear engineering Domino logic have become extremely popular in the design of today's high performance processors because they offer fast switching speeds compared to static CMOS circuits. However, scale down the domino logic requires t hreshold voltage reduction and supply voltage scaling to maintain the performance, but it increases the subthreshold leakage currents exponentially . To solve this problem, keeper transistor is introduced. Domino logic with standard keeper however still has a proble m with a contention current. In this project, domino logic with dynamic body biased keeper technique is proposed to achieve high performance domino logic in terms of speed and power dissipation. The new design is proposed by adding a sleep transis tor, reduces the capacitive by half to 1fF and also connects a new resistor, R a in series with the load resistor, R L . The proposed design of domino logic with dynamic body biased keeper shows improvement of average 37.60% in terms of speed, 67.89% in terms of power dissipation and 80.00% in terms of power delay product when compared to domino logic with standard keeper. Meanwhile, the design also manage to enhance speed by 26.72%, reduce power by 67.81% and reduce power delay product by 76.44 % comparing to previous DBBK circuit. Universiti Malaysia Sarawak, UNIMAS 2009 Final Year Project Report / IMRAD NonPeerReviewed text en http://ir.unimas.my/id/eprint/6537/1/Kiew%20Kwong%20ft.pdf Kiew,, Kwong Chwen. (2009) Performance of domino logic with dynamic body biased keeper. [Final Year Project Report / IMRAD] (Unpublished) |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Kiew,, Kwong Chwen. Performance of domino logic with dynamic body biased keeper |
| title | Performance of domino logic with dynamic body biased keeper |
| title_full | Performance of domino logic with dynamic body biased keeper |
| title_fullStr | Performance of domino logic with dynamic body biased keeper |
| title_full_unstemmed | Performance of domino logic with dynamic body biased keeper |
| title_short | Performance of domino logic with dynamic body biased keeper |
| title_sort | performance of domino logic with dynamic body biased keeper |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://ir.unimas.my/id/eprint/6537/ http://ir.unimas.my/id/eprint/6537/1/Kiew%20Kwong%20ft.pdf |