Design of buffer to drive large capacitive load with minimum delay

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Design of buffer to drive large capacitive load with minimum delay

The intention of this project is to design a cascade of inverters, known as buffer to drive a large capacitance load with a minimum delay. When moving toward the load, the delay time can be significantly reduced by cascading N numbers of inverters. Each inverter for each stage is larger by width, W...

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Bibliographic Details
Main Author:	Khadijah binti, Usaini
Format:	Final Year Project Report / IMRAD
Language:	English
Published:	University Malaysia Sarawak, UNIMAS. 2004
Subjects:	TJ Mechanical engineering and machinery TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://ir.unimas.my/id/eprint/2805/ http://ir.unimas.my/id/eprint/2805/1/Khadijah%20Usaini%20ft.pdf

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