Design of buffer to drive large capacitive load with minimum delay
The intention of this project is to design a cascade of inverters, known as buffer to drive a large capacitance load with a minimum delay. When moving toward the load, the delay time can be significantly reduced by cascading N numbers of inverters. Each inverter for each stage is larger by width, W...
| Main Author: | |
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| Format: | Final Year Project Report / IMRAD |
| Language: | English |
| Published: |
University Malaysia Sarawak, UNIMAS.
2004
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| Subjects: | |
| Online Access: | http://ir.unimas.my/id/eprint/2805/ http://ir.unimas.my/id/eprint/2805/1/Khadijah%20Usaini%20ft.pdf |
| _version_ | 1848835075367501824 |
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| author | Khadijah binti, Usaini |
| author_facet | Khadijah binti, Usaini |
| author_sort | Khadijah binti, Usaini |
| building | UNIMAS Institutional Repository |
| collection | Online Access |
| description | The intention of this project is to design a cascade of inverters, known as buffer to drive a large capacitance load with a minimum delay. When moving toward the load, the delay time can be significantly reduced by cascading N numbers of inverters. Each inverter for each stage is larger by width, W than the previous by a factor of stage ration, A. |
| first_indexed | 2025-11-15T06:02:06Z |
| format | Final Year Project Report / IMRAD |
| id | unimas-2805 |
| institution | Universiti Malaysia Sarawak |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T06:02:06Z |
| publishDate | 2004 |
| publisher | University Malaysia Sarawak, UNIMAS. |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | unimas-28052023-10-26T07:40:58Z http://ir.unimas.my/id/eprint/2805/ Design of buffer to drive large capacitive load with minimum delay Khadijah binti, Usaini TJ Mechanical engineering and machinery TK Electrical engineering. Electronics Nuclear engineering The intention of this project is to design a cascade of inverters, known as buffer to drive a large capacitance load with a minimum delay. When moving toward the load, the delay time can be significantly reduced by cascading N numbers of inverters. Each inverter for each stage is larger by width, W than the previous by a factor of stage ration, A. University Malaysia Sarawak, UNIMAS. 2004 Final Year Project Report / IMRAD NonPeerReviewed text en http://ir.unimas.my/id/eprint/2805/1/Khadijah%20Usaini%20ft.pdf Khadijah binti, Usaini (2004) Design of buffer to drive large capacitive load with minimum delay. [Final Year Project Report / IMRAD] (Unpublished) |
| spellingShingle | TJ Mechanical engineering and machinery TK Electrical engineering. Electronics Nuclear engineering Khadijah binti, Usaini Design of buffer to drive large capacitive load with minimum delay |
| title | Design of buffer to drive large capacitive load with minimum delay |
| title_full | Design of buffer to drive large capacitive load with minimum delay |
| title_fullStr | Design of buffer to drive large capacitive load with minimum delay |
| title_full_unstemmed | Design of buffer to drive large capacitive load with minimum delay |
| title_short | Design of buffer to drive large capacitive load with minimum delay |
| title_sort | design of buffer to drive large capacitive load with minimum delay |
| topic | TJ Mechanical engineering and machinery TK Electrical engineering. Electronics Nuclear engineering |
| url | http://ir.unimas.my/id/eprint/2805/ http://ir.unimas.my/id/eprint/2805/1/Khadijah%20Usaini%20ft.pdf |