Built in self test for RAM using VHDL
This project emphasized mainly on software analysis. Modelsim-Altera 6.4a is the software that used to generate every single module of the Built-in-Self-Test (BIST) for Random access Memory (RAM) architecture. There are three key things to be concern in the BIST for RAM which is the Test Pattern Gen...
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| Format: | Article |
| Language: | English |
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IEEE
2013
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| Online Access: | http://ir.unimas.my/id/eprint/16645/ http://ir.unimas.my/id/eprint/16645/1/Built%20in%20self%20test%20for%20RAM%20Using%20VHDL.pdf |
| _version_ | 1848838105427083264 |
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| author | Husin, M.H. Leong, S.Y. Sabri, M.F.M. |
| author_facet | Husin, M.H. Leong, S.Y. Sabri, M.F.M. |
| author_sort | Husin, M.H. |
| building | UNIMAS Institutional Repository |
| collection | Online Access |
| description | This project emphasized mainly on software analysis. Modelsim-Altera 6.4a is the software that used to generate every single module of the Built-in-Self-Test (BIST) for Random access Memory (RAM) architecture. There are three key things to be concern in the BIST for RAM which is the Test Pattern Generator (TPG), Output Response Analysis (ORA) and RAM. The output of counter which is a type of TPG is analyzed to provide a pattern for March test algorithm. At the mean time, the ORA compare the output from decoder and the RAM output itself which modeled under the theory of numerical autonomy of error vectors from the circuit under test. The output of ORA, the comparator, will show pass or fail for faulty detection of RAM. The system has been successfully developed and vector waveform is used to examine the result of the system. From the result obtained, it showed that the system is working as expected with satisfactory result. |
| first_indexed | 2025-11-15T06:50:16Z |
| format | Article |
| id | unimas-16645 |
| institution | Universiti Malaysia Sarawak |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T06:50:16Z |
| publishDate | 2013 |
| publisher | IEEE |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | unimas-166452017-06-14T07:22:34Z http://ir.unimas.my/id/eprint/16645/ Built in self test for RAM using VHDL Husin, M.H. Leong, S.Y. Sabri, M.F.M. TA Engineering (General). Civil engineering (General) This project emphasized mainly on software analysis. Modelsim-Altera 6.4a is the software that used to generate every single module of the Built-in-Self-Test (BIST) for Random access Memory (RAM) architecture. There are three key things to be concern in the BIST for RAM which is the Test Pattern Generator (TPG), Output Response Analysis (ORA) and RAM. The output of counter which is a type of TPG is analyzed to provide a pattern for March test algorithm. At the mean time, the ORA compare the output from decoder and the RAM output itself which modeled under the theory of numerical autonomy of error vectors from the circuit under test. The output of ORA, the comparator, will show pass or fail for faulty detection of RAM. The system has been successfully developed and vector waveform is used to examine the result of the system. From the result obtained, it showed that the system is working as expected with satisfactory result. IEEE 2013 Article PeerReviewed text en http://ir.unimas.my/id/eprint/16645/1/Built%20in%20self%20test%20for%20RAM%20Using%20VHDL.pdf Husin, M.H. and Leong, S.Y. and Sabri, M.F.M. (2013) Built in self test for RAM using VHDL. IEEE Colloquium on Humanities, Science and Engineering (CHUSER), 2012. ISSN ISBN: 978-1-4673-4617-7 http://ieeexplore.ieee.org/document/6504323/ DOI: 10.1109/CHUSER.2012.6504323 |
| spellingShingle | TA Engineering (General). Civil engineering (General) Husin, M.H. Leong, S.Y. Sabri, M.F.M. Built in self test for RAM using VHDL |
| title | Built in self test for RAM using VHDL |
| title_full | Built in self test for RAM using VHDL |
| title_fullStr | Built in self test for RAM using VHDL |
| title_full_unstemmed | Built in self test for RAM using VHDL |
| title_short | Built in self test for RAM using VHDL |
| title_sort | built in self test for ram using vhdl |
| topic | TA Engineering (General). Civil engineering (General) |
| url | http://ir.unimas.my/id/eprint/16645/ http://ir.unimas.my/id/eprint/16645/ http://ir.unimas.my/id/eprint/16645/ http://ir.unimas.my/id/eprint/16645/1/Built%20in%20self%20test%20for%20RAM%20Using%20VHDL.pdf |