Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits
State-of-the-art commercial placement tools have as goals to optimize area, timing, and power. Over the years, several reliability oriented placement strategies have been proposed with distinct goals, such as to improve the error rate. However, we found that there are still improvements that can be...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IOP Publishing
2017
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| Subjects: | |
| Online Access: | http://ir.unimas.my/id/eprint/15964/ http://ir.unimas.my/id/eprint/15964/1/Improved%20Multiple%20.pdf |
| _version_ | 1848837962296459264 |
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| author | Mohamad Imran, Bandan Pagliarini, Samuel Nascimento Mathew, Jimson Pradhan, Dhiraj K. |
| author_facet | Mohamad Imran, Bandan Pagliarini, Samuel Nascimento Mathew, Jimson Pradhan, Dhiraj K. |
| author_sort | Mohamad Imran, Bandan |
| building | UNIMAS Institutional Repository |
| collection | Online Access |
| description | State-of-the-art commercial placement tools have as goals to optimize area, timing, and power. Over the years, several reliability oriented placement strategies have been proposed with distinct goals, such as to improve the error rate. However, we found that there are still improvements that can be made for this type of approach, to improve not only the error rates but also the performance of the placer itself. Thus, this paper proposes several improvements toward an efficient multiple faults-aware placement strategy. First, an analytical method to profile pair of gates is proposed. Second, we add another level of optimization to reduce the amount of wirelength observed after the placement is completed without jeopardizing the main objective (reliability). Third, we propose a way to manipulate white spaces between gates smartly, to separate the gates that are profiled as the most likely to reduce the error rate when paired adjacently in the circuit. Results show that a wirelength reduction of up to 61% is achieved. Also, additional reduction of the error rate of up to 23% can be achieved with only an overhead on placement execution time. |
| first_indexed | 2025-11-15T06:47:59Z |
| format | Article |
| id | unimas-15964 |
| institution | Universiti Malaysia Sarawak |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T06:47:59Z |
| publishDate | 2017 |
| publisher | IOP Publishing |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | unimas-159642022-09-29T03:34:42Z http://ir.unimas.my/id/eprint/15964/ Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits Mohamad Imran, Bandan Pagliarini, Samuel Nascimento Mathew, Jimson Pradhan, Dhiraj K. T Technology (General) State-of-the-art commercial placement tools have as goals to optimize area, timing, and power. Over the years, several reliability oriented placement strategies have been proposed with distinct goals, such as to improve the error rate. However, we found that there are still improvements that can be made for this type of approach, to improve not only the error rates but also the performance of the placer itself. Thus, this paper proposes several improvements toward an efficient multiple faults-aware placement strategy. First, an analytical method to profile pair of gates is proposed. Second, we add another level of optimization to reduce the amount of wirelength observed after the placement is completed without jeopardizing the main objective (reliability). Third, we propose a way to manipulate white spaces between gates smartly, to separate the gates that are profiled as the most likely to reduce the error rate when paired adjacently in the circuit. Results show that a wirelength reduction of up to 61% is achieved. Also, additional reduction of the error rate of up to 23% can be achieved with only an overhead on placement execution time. IOP Publishing 2017-03 Article PeerReviewed text en http://ir.unimas.my/id/eprint/15964/1/Improved%20Multiple%20.pdf Mohamad Imran, Bandan and Pagliarini, Samuel Nascimento and Mathew, Jimson and Pradhan, Dhiraj K. (2017) Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits. IEEE Transactions on Reliability, 66 (1). pp. 233-244. ISSN 0018-9529 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85010660800&doi=10.1109%2fTR.2016.2643010&partnerID=40&md5=0bbf48890c97211f1d629aa421c6e59e doi:10.1088/1757-899X/205/1/012026 |
| spellingShingle | T Technology (General) Mohamad Imran, Bandan Pagliarini, Samuel Nascimento Mathew, Jimson Pradhan, Dhiraj K. Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits |
| title | Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits |
| title_full | Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits |
| title_fullStr | Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits |
| title_full_unstemmed | Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits |
| title_short | Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits |
| title_sort | improved multiple faults-aware placement strategy: reducing the overheads and error rates in digital circuits |
| topic | T Technology (General) |
| url | http://ir.unimas.my/id/eprint/15964/ http://ir.unimas.my/id/eprint/15964/ http://ir.unimas.my/id/eprint/15964/ http://ir.unimas.my/id/eprint/15964/1/Improved%20Multiple%20.pdf |