High throughput evaluation of SHA-1 implementation using unfolding transformation
Hash Function is widely used in the protocol scheme. In this paper, the design of SHA-1 hash function by using Verilog HDL based on FPGA is studied to optimise both hardware resource and performance. It was successfully synthesised and implemented using Altera Quartus II Arria II GX: EP2AGX45DF29C...
| Main Authors: | , |
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| Format: | Article |
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Asian Research Publishing Network (ARPN)
2016
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| Online Access: | http://ir.unimas.my/id/eprint/12162/ |
| _version_ | 1848837139536543744 |
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| author | Shamsiah, Binti Suhaili Takahiro, Watanabe |
| author_facet | Shamsiah, Binti Suhaili Takahiro, Watanabe |
| author_sort | Shamsiah, Binti Suhaili |
| building | UNIMAS Institutional Repository |
| collection | Online Access |
| description | Hash Function is widely used in the protocol scheme. In this paper, the design of SHA-1 hash function by using
Verilog HDL based on FPGA is studied to optimise both hardware resource and performance. It was successfully
synthesised and implemented using Altera Quartus II Arria II GX: EP2AGX45DF29C4. In this paper, two types of design
are proposed, namely SHA-1 and SHA-1unfolding. The maximum frequency of SHA-1 design is 274.2 MHz which is
higher than SHA-1 unfolding that has the maximum frequency of only 174.73 MHz. However, this leads to a high throughput of the SHA1 unfolding design with 2236.54 Mbps. Besides, both designs provide a small area implementation on Arria II that requires only 423 and 548 Combinational ALUTs, 693 and 907 total register, respectively |
| first_indexed | 2025-11-15T06:34:55Z |
| format | Article |
| id | unimas-12162 |
| institution | Universiti Malaysia Sarawak |
| institution_category | Local University |
| last_indexed | 2025-11-15T06:34:55Z |
| publishDate | 2016 |
| publisher | Asian Research Publishing Network (ARPN) |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | unimas-121622017-02-17T00:56:11Z http://ir.unimas.my/id/eprint/12162/ High throughput evaluation of SHA-1 implementation using unfolding transformation Shamsiah, Binti Suhaili Takahiro, Watanabe TA Engineering (General). Civil engineering (General) Hash Function is widely used in the protocol scheme. In this paper, the design of SHA-1 hash function by using Verilog HDL based on FPGA is studied to optimise both hardware resource and performance. It was successfully synthesised and implemented using Altera Quartus II Arria II GX: EP2AGX45DF29C4. In this paper, two types of design are proposed, namely SHA-1 and SHA-1unfolding. The maximum frequency of SHA-1 design is 274.2 MHz which is higher than SHA-1 unfolding that has the maximum frequency of only 174.73 MHz. However, this leads to a high throughput of the SHA1 unfolding design with 2236.54 Mbps. Besides, both designs provide a small area implementation on Arria II that requires only 423 and 548 Combinational ALUTs, 693 and 907 total register, respectively Asian Research Publishing Network (ARPN) 2016-03 Article PeerReviewed Shamsiah, Binti Suhaili and Takahiro, Watanabe (2016) High throughput evaluation of SHA-1 implementation using unfolding transformation. ARPN Journal of Engineering and Applied Sciences, 11 (5). pp. 3350-3355. ISSN 1819-6608 http://www.arpnjournals.org/jeas/research_papers/rp_2016/jeas_0316_3812.pdf |
| spellingShingle | TA Engineering (General). Civil engineering (General) Shamsiah, Binti Suhaili Takahiro, Watanabe High throughput evaluation of SHA-1 implementation using unfolding transformation |
| title | High throughput evaluation of SHA-1 implementation using unfolding transformation |
| title_full | High throughput evaluation of SHA-1 implementation using unfolding transformation |
| title_fullStr | High throughput evaluation of SHA-1 implementation using unfolding transformation |
| title_full_unstemmed | High throughput evaluation of SHA-1 implementation using unfolding transformation |
| title_short | High throughput evaluation of SHA-1 implementation using unfolding transformation |
| title_sort | high throughput evaluation of sha-1 implementation using unfolding transformation |
| topic | TA Engineering (General). Civil engineering (General) |
| url | http://ir.unimas.my/id/eprint/12162/ http://ir.unimas.my/id/eprint/12162/ |