Design and implementation of MD5 hash function algorithm using verilog HDL
Over the past 20 years, the demand of computers and the Internet has been increasing and people have paid a growing attention to information and network security. In result, various encryption algorithms coming into being. Cryptographic algorithm has become one of the most essential features of embe...
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| Format: | Conference or Workshop Item |
| Language: | English English |
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Springer Science and Business Media Deutschland GmbH
2022
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| Online Access: | http://umpir.ump.edu.my/id/eprint/39713/ http://umpir.ump.edu.my/id/eprint/39713/1/Design%20and%20Implementation%20of%20MD5%20Hash%20Function%20Algorithm.pdf http://umpir.ump.edu.my/id/eprint/39713/2/Design%20and%20implementation%20of%20MD5%20hash%20function%20algorithm%20using%20verilog%20HDL_ABS.pdf |
| _version_ | 1848825844821131264 |
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| author | Shamsiah, Suhaili Niam, Cleopatra Chundang Zainah, Md Zain Norhuzaimin, Julai |
| author_facet | Shamsiah, Suhaili Niam, Cleopatra Chundang Zainah, Md Zain Norhuzaimin, Julai |
| author_sort | Shamsiah, Suhaili |
| building | UMP Institutional Repository |
| collection | Online Access |
| description | Over the past 20 years, the demand of computers and the Internet has been increasing and people have paid a growing attention to information and network security. In result, various encryption algorithms coming into being. Cryptographic algorithm has become one of the most essential features of embedded system design. Hash functions are one of the cryptographies that can be used in both security design applications and protocol suites. A few distinct applications of hash algorithms are digital signatures, digital time stamping and the message integrity verification. Among hash algorithms, MD5 is the most used hash function algorithm. This paper proposed iterative looping architecture. The architecture includes MD5 padding block, data path, and a controller. A general concept and implementation of the MD5 hash function is described. The MD5 hash function modelling was done using Verilog, compiled with a few targeted virtual Altera Quartus devices, and simulated using ModelSim. Its performance in terms of frequency and throughput is compared with other MD5 implementations. The maximum frequency achieved is 111.45 MHz, and the throughput of iterative looping design was increased significantly to 864.58 Mbps using family device of Arria II GX. The improved performance of the implementation is the main goal of the design presented herein. |
| first_indexed | 2025-11-15T03:35:23Z |
| format | Conference or Workshop Item |
| id | ump-39713 |
| institution | Universiti Malaysia Pahang |
| institution_category | Local University |
| language | English English |
| last_indexed | 2025-11-15T03:35:23Z |
| publishDate | 2022 |
| publisher | Springer Science and Business Media Deutschland GmbH |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | ump-397132023-12-21T05:07:20Z http://umpir.ump.edu.my/id/eprint/39713/ Design and implementation of MD5 hash function algorithm using verilog HDL Shamsiah, Suhaili Niam, Cleopatra Chundang Zainah, Md Zain Norhuzaimin, Julai T Technology (General) TA Engineering (General). Civil engineering (General) TK Electrical engineering. Electronics Nuclear engineering Over the past 20 years, the demand of computers and the Internet has been increasing and people have paid a growing attention to information and network security. In result, various encryption algorithms coming into being. Cryptographic algorithm has become one of the most essential features of embedded system design. Hash functions are one of the cryptographies that can be used in both security design applications and protocol suites. A few distinct applications of hash algorithms are digital signatures, digital time stamping and the message integrity verification. Among hash algorithms, MD5 is the most used hash function algorithm. This paper proposed iterative looping architecture. The architecture includes MD5 padding block, data path, and a controller. A general concept and implementation of the MD5 hash function is described. The MD5 hash function modelling was done using Verilog, compiled with a few targeted virtual Altera Quartus devices, and simulated using ModelSim. Its performance in terms of frequency and throughput is compared with other MD5 implementations. The maximum frequency achieved is 111.45 MHz, and the throughput of iterative looping design was increased significantly to 864.58 Mbps using family device of Arria II GX. The improved performance of the implementation is the main goal of the design presented herein. Springer Science and Business Media Deutschland GmbH 2022 Conference or Workshop Item PeerReviewed pdf en http://umpir.ump.edu.my/id/eprint/39713/1/Design%20and%20Implementation%20of%20MD5%20Hash%20Function%20Algorithm.pdf pdf en http://umpir.ump.edu.my/id/eprint/39713/2/Design%20and%20implementation%20of%20MD5%20hash%20function%20algorithm%20using%20verilog%20HDL_ABS.pdf Shamsiah, Suhaili and Niam, Cleopatra Chundang and Zainah, Md Zain and Norhuzaimin, Julai (2022) Design and implementation of MD5 hash function algorithm using verilog HDL. In: Lecture Notes in Electrical Engineering; 12th National Technical Seminar on Unmanned System Technology, NUSYS 2020 , 24-25 November 2020 , Virtual, Online. pp. 499-510., 770 (266059). ISSN 1876-1100 ISBN 978-981162405-6 (Published) https://doi.org/10.1007/978-981-16-2406-3_38 |
| spellingShingle | T Technology (General) TA Engineering (General). Civil engineering (General) TK Electrical engineering. Electronics Nuclear engineering Shamsiah, Suhaili Niam, Cleopatra Chundang Zainah, Md Zain Norhuzaimin, Julai Design and implementation of MD5 hash function algorithm using verilog HDL |
| title | Design and implementation of MD5 hash function algorithm using verilog HDL |
| title_full | Design and implementation of MD5 hash function algorithm using verilog HDL |
| title_fullStr | Design and implementation of MD5 hash function algorithm using verilog HDL |
| title_full_unstemmed | Design and implementation of MD5 hash function algorithm using verilog HDL |
| title_short | Design and implementation of MD5 hash function algorithm using verilog HDL |
| title_sort | design and implementation of md5 hash function algorithm using verilog hdl |
| topic | T Technology (General) TA Engineering (General). Civil engineering (General) TK Electrical engineering. Electronics Nuclear engineering |
| url | http://umpir.ump.edu.my/id/eprint/39713/ http://umpir.ump.edu.my/id/eprint/39713/ http://umpir.ump.edu.my/id/eprint/39713/1/Design%20and%20Implementation%20of%20MD5%20Hash%20Function%20Algorithm.pdf http://umpir.ump.edu.my/id/eprint/39713/2/Design%20and%20implementation%20of%20MD5%20hash%20function%20algorithm%20using%20verilog%20HDL_ABS.pdf |