Selective harmonic elimination using MFO for a reduced switch multi-level inverter topology

Selective harmonic elimination using MFO for a reduced switch multi-level inverter topology

This research article proposed a new modified single-phase multi-level inverter topology with an optimal switching control strategy to reduce the inverter output harmonic distortion. The topology is configured to operate in asymmetric mode to generate eleven levels of output voltage steps. Additiona...

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Bibliographic Details
Main Authors: Shanono, Ibrahim Haruna, Nor Rul Hasma, Abdullah, Hamdan, Daniyal, Aisha, Muhammad
Format: Conference or Workshop Item
Language:English
English
Published: Institute of Electrical and Electronics Engineers Inc. 2022
Subjects:
T Technology (General)
TA Engineering (General). Civil engineering (General)
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://umpir.ump.edu.my/id/eprint/39411/
http://umpir.ump.edu.my/id/eprint/39411/1/Selective%20Harmonic%20Elimination%20using%20MFO%20for%20a%20Reduced%20Switch.pdf
http://umpir.ump.edu.my/id/eprint/39411/2/Selective%20harmonic%20elimination%20using%20MFO%20for%20a%20reduced%20switch%20multi-level%20inverter%20topology_ABS.pdf

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