Optimization of n-MOS 6T nanowire SRAM bit cell based on nanowires ratio of SiNWTs

Optimization of n-MOS 6T nanowire SRAM bit cell based on nanowires ratio of SiNWTs

In nowadays technology, the primary memory structure widely used in many digital circuit applications is a six transistor (6T) Static Random Access Memory (SRAM) bit cell. The main reason for minimizing memory bit cell to nanodimensions is to provide the SRAM integrated circuits (ICs) with the possi...

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Bibliographic Details
Main Authors: Hashim, Yasir, Jabbar, Waheb A.
Format: Article
Language:English
Published: Sumy State University 2020
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://umpir.ump.edu.my/id/eprint/30511/
http://umpir.ump.edu.my/id/eprint/30511/1/Optimization%20of%20n-MOS%206T%20nanowire%20SRAM%20bit%20cell.pdf

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