Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor
This study explores optimization of resistance load (R-Load) of four silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. Noise margins and inflection voltage of butterfly characteristics with static power consumption of SRAM cell are used as limiting factors in this op...
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| Format: | Article |
| Language: | English English |
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American Scientific Publishers
2018
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| Online Access: | http://umpir.ump.edu.my/id/eprint/19249/ http://umpir.ump.edu.my/id/eprint/19249/1/17JNN-13956.pdf http://umpir.ump.edu.my/id/eprint/19249/7/ftech-2018-yasir.pdf |
| _version_ | 1848820861515071488 |
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| author | Hashim, Yasir |
| author_facet | Hashim, Yasir |
| author_sort | Hashim, Yasir |
| building | UMP Institutional Repository |
| collection | Online Access |
| description | This study explores optimization of resistance load (R-Load) of four silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. Noise margins and inflection voltage of butterfly characteristics with static power consumption of SRAM cell are used as limiting factors in this optimization. Range of R-Load used in this study was 20–1000 KΩ with V dd= 1 V. Results indicate that optimization depends critically on resistance load value. The optimized range of R-Load is 100–200 KΩ. |
| first_indexed | 2025-11-15T02:16:11Z |
| format | Article |
| id | ump-19249 |
| institution | Universiti Malaysia Pahang |
| institution_category | Local University |
| language | English English |
| last_indexed | 2025-11-15T02:16:11Z |
| publishDate | 2018 |
| publisher | American Scientific Publishers |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | ump-192492018-03-07T07:05:33Z http://umpir.ump.edu.my/id/eprint/19249/ Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor Hashim, Yasir TK Electrical engineering. Electronics Nuclear engineering This study explores optimization of resistance load (R-Load) of four silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. Noise margins and inflection voltage of butterfly characteristics with static power consumption of SRAM cell are used as limiting factors in this optimization. Range of R-Load used in this study was 20–1000 KΩ with V dd= 1 V. Results indicate that optimization depends critically on resistance load value. The optimized range of R-Load is 100–200 KΩ. American Scientific Publishers 2018-02 Article PeerReviewed application/pdf en http://umpir.ump.edu.my/id/eprint/19249/1/17JNN-13956.pdf application/pdf en http://umpir.ump.edu.my/id/eprint/19249/7/ftech-2018-yasir.pdf Hashim, Yasir (2018) Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor. Journal of Nanoscience and Nanotechnology, 18 (2). pp. 1199-1201. ISSN 1533-4880 (Print); 1533-4899 (Online). (Published) https://doi.org/10.1166/jnn.2018.13956 https://doi.org/10.1166/jnn.2018.13956 |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Hashim, Yasir Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor |
| title | Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor |
| title_full | Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor |
| title_fullStr | Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor |
| title_full_unstemmed | Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor |
| title_short | Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor |
| title_sort | optimization of resistance load in 4t-static random-access memory cell based on silicon nanowire transistor |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://umpir.ump.edu.my/id/eprint/19249/ http://umpir.ump.edu.my/id/eprint/19249/ http://umpir.ump.edu.my/id/eprint/19249/ http://umpir.ump.edu.my/id/eprint/19249/1/17JNN-13956.pdf http://umpir.ump.edu.my/id/eprint/19249/7/ftech-2018-yasir.pdf |