Optimization of Channel Length Nano-Scale SiNWT Based SRAM Cell
This paper represents a channel length ratio optimization at a different high logic level voltage for 6-Silicon Nanowire Transistors (SiNWT) SRAM cell. This study is the first to demonstrate an optimized length ratio of nanowires with different Vdd of nano-scale SiNWT based SRAM cell. Noise margins...
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| Format: | Conference or Workshop Item |
| Language: | English |
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American Institute of Physics (AIP)
2016
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| Online Access: | http://umpir.ump.edu.my/id/eprint/15319/ http://umpir.ump.edu.my/id/eprint/15319/1/1.4965107.pdf_expires%3D1479185924%26id%3Did%26accname%3Dguest%26checksum%3DB61DB192446CC5D114088756A852C2F6 |
| _version_ | 1848819925505802240 |
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| author | Naif, Yasir Hashim |
| author_facet | Naif, Yasir Hashim |
| author_sort | Naif, Yasir Hashim |
| building | UMP Institutional Repository |
| collection | Online Access |
| description | This paper represents a channel length ratio optimization at a different high logic level voltage for 6-Silicon Nanowire Transistors (SiNWT) SRAM cell. This study is the first to demonstrate an optimized length ratio of nanowires with different Vdd of nano-scale SiNWT based SRAM cell. Noise margins (NM) and inflection voltage (Vinf) of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both length ratios of nanowires and logic voltage level (Vdd), and increasing of high logic voltage level of the SiNWT based SRAM cell tends to decrease in the optimized nanowires length ratio with decreasing in current and power. |
| first_indexed | 2025-11-15T02:01:18Z |
| format | Conference or Workshop Item |
| id | ump-15319 |
| institution | Universiti Malaysia Pahang |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T02:01:18Z |
| publishDate | 2016 |
| publisher | American Institute of Physics (AIP) |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | ump-153192017-08-22T06:51:25Z http://umpir.ump.edu.my/id/eprint/15319/ Optimization of Channel Length Nano-Scale SiNWT Based SRAM Cell Naif, Yasir Hashim TK Electrical engineering. Electronics Nuclear engineering This paper represents a channel length ratio optimization at a different high logic level voltage for 6-Silicon Nanowire Transistors (SiNWT) SRAM cell. This study is the first to demonstrate an optimized length ratio of nanowires with different Vdd of nano-scale SiNWT based SRAM cell. Noise margins (NM) and inflection voltage (Vinf) of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both length ratios of nanowires and logic voltage level (Vdd), and increasing of high logic voltage level of the SiNWT based SRAM cell tends to decrease in the optimized nanowires length ratio with decreasing in current and power. American Institute of Physics (AIP) 2016-10-19 Conference or Workshop Item PeerReviewed application/pdf en http://umpir.ump.edu.my/id/eprint/15319/1/1.4965107.pdf_expires%3D1479185924%26id%3Did%26accname%3Dguest%26checksum%3DB61DB192446CC5D114088756A852C2F6 Naif, Yasir Hashim (2016) Optimization of Channel Length Nano-Scale SiNWT Based SRAM Cell. In: AIP Conference Proceeding: International Conference on Advanced Science, Engineering and Technology (ICASET 2015) , 21-22 December 2015 , Penang, Malaysia. pp. 1-7., 1774 (050020). ISBN 978-0-7354-1432-7 (Published) http://dx.doi.org/10.1063/1.4965107 10.1063/1.4965107 |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Naif, Yasir Hashim Optimization of Channel Length Nano-Scale SiNWT Based SRAM Cell |
| title | Optimization of Channel Length Nano-Scale SiNWT Based SRAM Cell |
| title_full | Optimization of Channel Length Nano-Scale SiNWT Based SRAM Cell |
| title_fullStr | Optimization of Channel Length Nano-Scale SiNWT Based SRAM Cell |
| title_full_unstemmed | Optimization of Channel Length Nano-Scale SiNWT Based SRAM Cell |
| title_short | Optimization of Channel Length Nano-Scale SiNWT Based SRAM Cell |
| title_sort | optimization of channel length nano-scale sinwt based sram cell |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://umpir.ump.edu.my/id/eprint/15319/ http://umpir.ump.edu.my/id/eprint/15319/ http://umpir.ump.edu.my/id/eprint/15319/ http://umpir.ump.edu.my/id/eprint/15319/1/1.4965107.pdf_expires%3D1479185924%26id%3Did%26accname%3Dguest%26checksum%3DB61DB192446CC5D114088756A852C2F6 |