A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor
This study explores dimensional optimization at different high logic-level voltages for six silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. This study is the first to demonstrate diameter and length of nanowires with different logic voltage level (Vdd) optimization...
| Main Author: | Hashim, Yasir |
|---|---|
| Format: | Article |
| Language: | English English |
| Published: |
American Scientific Publishers
2017
|
| Subjects: | |
| Online Access: | http://umpir.ump.edu.my/id/eprint/15045/ http://umpir.ump.edu.my/id/eprint/15045/1/16JNN-12608.pdf http://umpir.ump.edu.my/id/eprint/15045/7/ftech-yasir-2017.pdf |
Similar Items
Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor
by: Hashim, Yasir
Published: (2018)
by: Hashim, Yasir
Published: (2018)
Design And Characterization Of Silicon Nanowire Transistor And Logic Nanowire Inverter Circuits
by: Naif, Yasir Hashim
Published: (2013)
by: Naif, Yasir Hashim
Published: (2013)
Characterization of silicon nanowire transistor
by: Al Ariqi, Hani Taha, et al.
Published: (2019)
by: Al Ariqi, Hani Taha, et al.
Published: (2019)
A new factor for fabrication technologies evaluation for silicon nanowire transistors
by: Hashim, Yasir, et al.
Published: (2020)
by: Hashim, Yasir, et al.
Published: (2020)
A new factor for fabrication technologies evaluation for silicon nanowire transistors.
by: yasir, Hashim, et al.
Published: (2020)
by: yasir, Hashim, et al.
Published: (2020)
Temperature characteristics of silicon nanowire transistor depending on oxide thickness
by: AlAriqi, Hani Taha, et al.
Published: (2019)
by: AlAriqi, Hani Taha, et al.
Published: (2019)
Temperature sensitivity of silicon nanowire transistor based on channel length
by: AlAriqi, Hani Taha, et al.
Published: (2019)
by: AlAriqi, Hani Taha, et al.
Published: (2019)
Nanowire NMOS Logic Inverter Characterization
by: Naif, Yasir Hashim
Published: (2016)
by: Naif, Yasir Hashim
Published: (2016)
Etching Effect On The Formation Of Silicon Nanowire Transistor Patterned By AFM Lithography.
by: Abdullah, A. Makarimi, et al.
Published: (2010)
by: Abdullah, A. Makarimi, et al.
Published: (2010)
Electrical and temperature characterisation of silicon and germanium nanowire transistors based on channel dimensions
by: Hani Taha, Abd Assamad Al Ariqi
Published: (2020)
by: Hani Taha, Abd Assamad Al Ariqi
Published: (2020)
A New Simulation Model for Nanowire-CMOS Inverter Circuit
by: Naif, Yasir Hashim
Published: (2016)
by: Naif, Yasir Hashim
Published: (2016)
Optimization of n-MOS 6T nanowire SRAM bit cell based on nanowires ratio of SiNWTs
by: Hashim, Yasir, et al.
Published: (2020)
by: Hashim, Yasir, et al.
Published: (2020)
Optimization of Nanowire Resistance Load Logic Inverter
by: Naif, Yasir Hashim, et al.
Published: (2015)
by: Naif, Yasir Hashim, et al.
Published: (2015)
Fabrication and simulation of lithographically defined junctionless lateral gate silicon nanowire transistors
by: Larki, Farhad
Published: (2012)
by: Larki, Farhad
Published: (2012)
Optimization Of Potassium Hydroxide (KOH) Etching On The Fabrication Of P-Type Silicon Nanowire Transistor Patterned By Atomic Force Microscopy Lithography
by: Abdullah, Ahmad Makarimi
Published: (2012)
by: Abdullah, Ahmad Makarimi
Published: (2012)
Effect of TMAH etching duration on the formation of silicon nanowire transistor patterned by AFM nanolithography
by: Sabar Hutagalung, D., et al.
Published: (2012)
by: Sabar Hutagalung, D., et al.
Published: (2012)
Effect Of Tetramethylammonium Hydroxide (TMAH) Etchant On The Formation Of Silicon Nanowires Transistor Patterned By Atomic Force Microscopy (AFM)
Lithography
by: Lew, Kam Chung
Published: (2011)
by: Lew, Kam Chung
Published: (2011)
Fabrication and simulation of P-type junctionless silicon nanowire transistor using silicon on insulator and atomic force microscope nano lithography
by: Dehzangi, Arash
Published: (2012)
by: Dehzangi, Arash
Published: (2012)
Development of automated neighborhood pattern sensitive faults syndrome generator for static random access memory
by: Rusli, Julie Roslita
Published: (2011)
by: Rusli, Julie Roslita
Published: (2011)
March-based diagnosis algorithm for static random-access memory stuck-at faults and transition faults
by: Mat Isa, Masnita
Published: (2012)
by: Mat Isa, Masnita
Published: (2012)
Nano-dimensional properties of Si-FinFET transistor based on ION/IOFF ratio and subthreshold swing (SS)
by: Mahmood, Ahmed, et al.
Published: (2018)
by: Mahmood, Ahmed, et al.
Published: (2018)
A Review on Transistors in Nano Dimensions
by: Naif, Yasir Hashim
Published: (2015)
by: Naif, Yasir Hashim
Published: (2015)
Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) based ternary combinational logic circuits
by: Zahoor, Furqan, et al.
Published: (2021)
by: Zahoor, Furqan, et al.
Published: (2021)
Optimal Nano-Dimensional Channel of GaAs-FinFET Transistor
by: Mahmood, Ahmed, et al.
Published: (2018)
by: Mahmood, Ahmed, et al.
Published: (2018)
Optimization Of Potassium Hydroxide (Koh) Etching On The Fabrication Of P-Type Silicon Nanowire Transistor Patterned By Atomic Force Microscopy Lithography
by: Abdullah, Ahmad Makarimi
Published: (2012)
by: Abdullah, Ahmad Makarimi
Published: (2012)
Temperature Effect on ON/OFF Current Ratio of FinFET Transistor
by: Hashim, Yasir
Published: (2017)
by: Hashim, Yasir
Published: (2017)
Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic force microscopy nanolithography
by: Dehzangi, Arash, et al.
Published: (2013)
by: Dehzangi, Arash, et al.
Published: (2013)
Electrical characterisation of highly doped triangular silicon nanowires
by: Za'bah, Nor Farahidah, et al.
Published: (2014)
by: Za'bah, Nor Farahidah, et al.
Published: (2014)
Study the characteristic of p-type junction-less side gate silicon nanowire transistor fabricated by atomic force microscopy lithography
by: Dehzangi, Arash, et al.
Published: (2011)
by: Dehzangi, Arash, et al.
Published: (2011)
SOI based nanowire single-electron transistors: design, simulation and process development
by: Hashim, Uda, et al.
Published: (2007)
by: Hashim, Uda, et al.
Published: (2007)
Aloe-Polysaccharides Thin Film As All-Natural And Flexible Resistive Random Access Memory
by: Yeap, Kee Leong
Published: (2018)
by: Yeap, Kee Leong
Published: (2018)
A fault syndromes simulator for random access memories
by: Wan Hasan, Wan Zuha, et al.
Published: (2008)
by: Wan Hasan, Wan Zuha, et al.
Published: (2008)
Design and fabrication of silicon nanowire based sensor
by: Abd Rahman, Siti Fatimah, et al.
Published: (2013)
by: Abd Rahman, Siti Fatimah, et al.
Published: (2013)
Applicability Of Analytical Model For Modeling Silicon And Silicon Carbide MOS Transistors
by: Lock, Choon Hou
Published: (2006)
by: Lock, Choon Hou
Published: (2006)
Design Of 1K Asynchronous Static Random Access Memory Using 0.35 Micron Complementary Metal Oxide Semiconductor Technology
by: Yeong, Tak Nging
Published: (2005)
by: Yeong, Tak Nging
Published: (2005)
Pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography
by: Larki, Farhad, et al.
Published: (2013)
by: Larki, Farhad, et al.
Published: (2013)
Temperature sensitivity based on channel length of FinFET transistor
by: Atalla, Yousif, et al.
Published: (2018)
by: Atalla, Yousif, et al.
Published: (2018)
Synthesis Of Silicon Nanowires By Carbothermal Evaporation Method Using Metal Catalyst
by: Bahrin, Muhamad Dzulnawarin Kamal
Published: (2017)
by: Bahrin, Muhamad Dzulnawarin Kamal
Published: (2017)
Analysis of silicon nanowires synthesized from SIO on silicon wafer substrate
by: Hamidinezhad, Habib, et al.
Published: (2009)
by: Hamidinezhad, Habib, et al.
Published: (2009)
Silicon nanowire interface circuit for DNA detection
by: Usman, Kamilu Iman, et al.
Published: (2017)
by: Usman, Kamilu Iman, et al.
Published: (2017)
Similar Items
-
Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor
by: Hashim, Yasir
Published: (2018) -
Design And Characterization Of Silicon Nanowire Transistor And Logic Nanowire Inverter Circuits
by: Naif, Yasir Hashim
Published: (2013) -
Characterization of silicon nanowire transistor
by: Al Ariqi, Hani Taha, et al.
Published: (2019) -
A new factor for fabrication technologies evaluation for silicon nanowire transistors
by: Hashim, Yasir, et al.
Published: (2020) -
A new factor for fabrication technologies evaluation for silicon nanowire transistors.
by: yasir, Hashim, et al.
Published: (2020)