Diameter Optimization of Nano-scale SiNWT Based SRAM Cell
This paper represents diameter and logic voltage level optimizations of 6-Silicon Nanowire Transistors (SiNWT) SRAM. This study is to demonstrate diameter of nanowires effects at a different logic voltage level (Vdd) on the static characteristics of Nano-scale SiNWT Based SRAM Cell. Noise margins (N...
| Main Authors: | , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2015
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| Subjects: | |
| Online Access: | http://umpir.ump.edu.my/id/eprint/11635/ http://umpir.ump.edu.my/id/eprint/11635/1/ICCSCE2015%20Paper.pdf |
| _version_ | 1848819055486566400 |
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| author | Naif, Yasir Hashim Hadi, Manap |
| author_facet | Naif, Yasir Hashim Hadi, Manap |
| author_sort | Naif, Yasir Hashim |
| building | UMP Institutional Repository |
| collection | Online Access |
| description | This paper represents diameter and logic voltage level optimizations of 6-Silicon Nanowire Transistors (SiNWT) SRAM. This study is to demonstrate diameter of nanowires effects at a different logic voltage level (Vdd) on the static characteristics of Nano-scale SiNWT Based SRAM Cell. Noise margins (NM) and inflection voltage (Vinf) of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both diameters of nanowires and logic voltage level (Vdd). And increasing of logic voltage level from 1V to 3V tends to decrease in optimized nanowires diameters but with increasing in current and power dissipation. SRAM using nanowires transistors must use logic level (2V or 2.5V) to produce SRAM with lower diameters and suitable inflection currents and then with lower power dissipation as possible. |
| first_indexed | 2025-11-15T01:47:28Z |
| format | Conference or Workshop Item |
| id | ump-11635 |
| institution | Universiti Malaysia Pahang |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T01:47:28Z |
| publishDate | 2015 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | ump-116352018-02-07T06:31:10Z http://umpir.ump.edu.my/id/eprint/11635/ Diameter Optimization of Nano-scale SiNWT Based SRAM Cell Naif, Yasir Hashim Hadi, Manap QC Physics TK Electrical engineering. Electronics Nuclear engineering This paper represents diameter and logic voltage level optimizations of 6-Silicon Nanowire Transistors (SiNWT) SRAM. This study is to demonstrate diameter of nanowires effects at a different logic voltage level (Vdd) on the static characteristics of Nano-scale SiNWT Based SRAM Cell. Noise margins (NM) and inflection voltage (Vinf) of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both diameters of nanowires and logic voltage level (Vdd). And increasing of logic voltage level from 1V to 3V tends to decrease in optimized nanowires diameters but with increasing in current and power dissipation. SRAM using nanowires transistors must use logic level (2V or 2.5V) to produce SRAM with lower diameters and suitable inflection currents and then with lower power dissipation as possible. 2015-11 Conference or Workshop Item PeerReviewed application/pdf en http://umpir.ump.edu.my/id/eprint/11635/1/ICCSCE2015%20Paper.pdf Naif, Yasir Hashim and Hadi, Manap (2015) Diameter Optimization of Nano-scale SiNWT Based SRAM Cell. In: 2015 IEEE International Conference on Control System, Computing and Engineering , 27 - 29 November 2015 , Penang, Malaysia. pp. 87-90.. (Published) http://iccsce.acscrg.com/ |
| spellingShingle | QC Physics TK Electrical engineering. Electronics Nuclear engineering Naif, Yasir Hashim Hadi, Manap Diameter Optimization of Nano-scale SiNWT Based SRAM Cell |
| title | Diameter Optimization of Nano-scale SiNWT Based SRAM Cell |
| title_full | Diameter Optimization of Nano-scale SiNWT Based SRAM Cell |
| title_fullStr | Diameter Optimization of Nano-scale SiNWT Based SRAM Cell |
| title_full_unstemmed | Diameter Optimization of Nano-scale SiNWT Based SRAM Cell |
| title_short | Diameter Optimization of Nano-scale SiNWT Based SRAM Cell |
| title_sort | diameter optimization of nano-scale sinwt based sram cell |
| topic | QC Physics TK Electrical engineering. Electronics Nuclear engineering |
| url | http://umpir.ump.edu.my/id/eprint/11635/ http://umpir.ump.edu.my/id/eprint/11635/ http://umpir.ump.edu.my/id/eprint/11635/1/ICCSCE2015%20Paper.pdf |