VHDL description for IP Engine / Zeliall Bathich
Developing hardware support for network layer protocol processing is a very complex and demanding task. However. for optimal performance hardware acceleration can be required. To cope with the situation. this project present a high-level design approach. which targets the development of configurable...
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| Format: | Thesis |
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2000
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| Online Access: | http://studentsrepo.um.edu.my/9932/ http://studentsrepo.um.edu.my/9932/1/Zeliall_Bathich_%2D_Academic_exercise.pdf |
| _version_ | 1848774033896636416 |
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| author | Zeliall, Bathich |
| author_facet | Zeliall, Bathich |
| author_sort | Zeliall, Bathich |
| building | UM Research Repository |
| collection | Online Access |
| description | Developing hardware support for network layer protocol processing is a very complex and demanding task. However. for optimal performance hardware acceleration can be required. To cope with the situation. this project present a high-level design approach. which targets the development of configurable and reusable components. Therefore it obtains the integration of advanced tools for the development of the IP Engine into the design environment. This process is illustrated based on a TCP/IP header analysis and validation component for which initial performance results are presented. The development of this Engine is embedded in an approach to develop flexible and configurable protocol engines that can be optimized for specific application. By implementing the IP Engine in hardware it will help reducing communication bottlenecks replacing expensive software solutions. which are based on 32 bit processor cores. With its small footprint design it will improve low power-consumption. Highly cost-effective solution to Perform all protocol functions of TCP/IP and UDP/IP connections for sustained bit rates of up to 100 Mbps independent of packet payload sizes and other connection parameters. |
| first_indexed | 2025-11-14T13:51:52Z |
| format | Thesis |
| id | um-9932 |
| institution | University Malaya |
| institution_category | Local University |
| last_indexed | 2025-11-14T13:51:52Z |
| publishDate | 2000 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | um-99322020-08-16T23:20:37Z VHDL description for IP Engine / Zeliall Bathich Zeliall, Bathich QA75 Electronic computers. Computer science Developing hardware support for network layer protocol processing is a very complex and demanding task. However. for optimal performance hardware acceleration can be required. To cope with the situation. this project present a high-level design approach. which targets the development of configurable and reusable components. Therefore it obtains the integration of advanced tools for the development of the IP Engine into the design environment. This process is illustrated based on a TCP/IP header analysis and validation component for which initial performance results are presented. The development of this Engine is embedded in an approach to develop flexible and configurable protocol engines that can be optimized for specific application. By implementing the IP Engine in hardware it will help reducing communication bottlenecks replacing expensive software solutions. which are based on 32 bit processor cores. With its small footprint design it will improve low power-consumption. Highly cost-effective solution to Perform all protocol functions of TCP/IP and UDP/IP connections for sustained bit rates of up to 100 Mbps independent of packet payload sizes and other connection parameters. 2000 Thesis NonPeerReviewed application/pdf http://studentsrepo.um.edu.my/9932/1/Zeliall_Bathich_%2D_Academic_exercise.pdf Zeliall, Bathich (2000) VHDL description for IP Engine / Zeliall Bathich. Undergraduates thesis, University of Malaya. http://studentsrepo.um.edu.my/9932/ |
| spellingShingle | QA75 Electronic computers. Computer science Zeliall, Bathich VHDL description for IP Engine / Zeliall Bathich |
| title | VHDL description for IP Engine / Zeliall Bathich |
| title_full | VHDL description for IP Engine / Zeliall Bathich |
| title_fullStr | VHDL description for IP Engine / Zeliall Bathich |
| title_full_unstemmed | VHDL description for IP Engine / Zeliall Bathich |
| title_short | VHDL description for IP Engine / Zeliall Bathich |
| title_sort | vhdl description for ip engine / zeliall bathich |
| topic | QA75 Electronic computers. Computer science |
| url | http://studentsrepo.um.edu.my/9932/ http://studentsrepo.um.edu.my/9932/1/Zeliall_Bathich_%2D_Academic_exercise.pdf |