Degradation analysis based on design considerations of advanced-process MOSFET / Ainul Fatin Muhammad Alimin - Ainul Fatin, Muhammad Alimin (2018)
The unceasing scaling of complementary metal-oxide-semiconductor (CMOS) technology has contributed to the steady increase in transistors performance for the past decades. However, it will also increase the power densities which will eventually leads to the increase in temperatures and other scaling effects, thus decrementing the lifetime reliability of transistors in the long-term usage. Reliability issues such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) impose challenges in the designing of CMOS devices as the device feature size enters the nanoscale regime. Therefore, there is a need to study the mechanism of the defects transformation process due to the variation of design considerations in the advanced-process CMOS devices in order to develop an effective aging aware design. This work presents a comprehensive simulation study on the effect of design considerations of the 32 nm advanced-process high-k p-channel metal-oxide-semiconductor field-effect transistor (pMOSFET) and n-channel laterally diffused metal-oxide-semiconductor (nLDMOS) with STI based structure on NBTI and HCI respectively. The design structures and analysis were simulated using Synopsis Sentaurus Technology Computer-Aided Design (TCAD) simulator based on standard CMOS manufacturing trends. This study composed of two parts. The first part focuses on the NBTI reliability issue where NBTI mechanism and defects were explored through varied design parameters of extensively wide range of values. NBTI simulation measurement in this work follows the on-the-fly (OTF) method to capture the mechanisms of the fast and slow traps. NBTI study in this work elaborates on the dependency of the threshold voltage (Vth) degradation on stress oxide field, stress temperature as well as investigation on the devices’ Arrhenius plot. The second part of this study addresses the HCI reliability issue in nLDMOS devices. The design parameters were varied in order to investigate the influence of these parameters on HCI. The nLDMOS device degradation due to HCI was simulated using stress-measure testing technique. The electrical analysis performed displays detailed insight into the impact ionization rate and electric field distribution apart from the on-resistance (Ron) and I-V characterization. From the NBTI study, it is found that the Vth degradation analysis at 1ks and 375K shows that changing the SiO2 interfacial layer thickness affects the Vth degradation by 96.16% more than changing the HfO2 thickness and by 80.67% more than changing the metal gate thickness. It is also found that the NBTI effect depends on process design considerations, where it was observed that higher boron dose and high metal work function may lead to higher Vth degradation. However, the halo doping concentration in the advanced 32 nm structure has an insignificant effect on NBTI. The HCI study shows that the drain current for device with 100⁰ STI angle is reduced by 58.78% compared to device with 45⁰ STI angle. Larger STI angle shows higher HCI degradation while larger STI depth as well as larger gate oxide thickness is observed to cause lower degradation. Process design wise, it is found that higher p-substrate doping concentration exhibit higher degradation and the HCI degradation is not significantly affected by the S/D implantation dose.