Characterization of pMosfet degradation in negative bias temperature instability test / Soon Foo Yew - Soon, Foo Yew (2012)
Threshold voltage instability has become a major IC reliability concern for sub-micron CMOS process technology. In the past, VTH Stability test is commonly used by the wafer fabrication plant to have a quick assessment on this reliability concern during process qualification, due to its simple test procedure. In recent years, Negative Bias Temperature Instability (NBTI) test has been used extensively to characterize not only the threshold voltage, but also other transistor parameters. The NBTI test consists of interim measurements at high temperature during stress, allowing degradation behavior to be studied in more detail than VTH Stability test. This experimental study has demonstrated the capability in measuring transistor parametric at high temperature for NBTI characterization. The conventional DC NBTI stress tests are performed on 0.18 μm pMOSFET with a gate oxide thickness of 2.9 nm, fabricated on 0.18 μm Dual Gate CMOS process. Data analysis on parametric degradation behavior indicates that increase in interface states play a dominant role and the extracted n exponent matches the analytically derived value from the Reaction-Diffusion model. Also, the results from this conventional DC NBTI stress show that degradation seen on saturation mode is less severe than the degradation on linear mode of pMOSFET operation. This is further confirmed by analysis of lifetime extrapolation which shows the IDSAT (saturation mode) lifetime is 2 order of magnitudes higher than VTEXT/VTCI (linear mode) lifetime. Additional analysis shows that VTCI is the most sensitive parameter to be monitored during NBTI stress and will be used as the key parameter in the later stage of this experimental study. From further experimental work, it can be seen that NBTI test allows a deeper understanding of pMOSFET parametric degradation behavior than VTH Stability test, that shows a strong dependence of NBTI degradation on temperature, channel length and gate oxide thickness variation. In addition, the proposed Optimized ID-VG sweep measurement method is shown to generate a more accurate lifetime extraction and can easily be implemented in wafer fabrication plant without additional hardware or software. This method is applicable for process development, process qualification and periodical monitoring for NBTI degradation performance during mass production.