Design of low power, high linearity down-conversion CMOS mixer for industrial, scientific and medical applications at 900 MHz / Lai Chi Yi - Lai, Chi Yi (2021)
In the tremendous growth of wireless application, low voltage and low power consumption with high linearity become a major consideration in radio frequency integrated circuit (RFIC). The development of a low power RF transceiver is driven in the demand of withstanding longer battery life and reduced cost to move towards mobile application. The continuous downscaling of CMOS technologies to reduce overall power consumption and high speed operation imposes design challenges in the construction of RF front end blocks, which creates an environment where circuits requires lesser voltage headroom to operate. This has driven the need in exploration of new low voltage and high linearity design technique for RF architecture. Often folded cascode topology is preferred over series stacking topology due to voltage headroom limitation. This work proposes new design and implementation of low voltage and low power down-conversion mixer with high linearity in 0.13?m standard CMOS technology for 900 MHz ISM applications. The proposed mixer performs frequency translation from a 900 MHz input radio frequency (RF) signal to a 100 MHz output intermediate frequency (IF) signal referring to a 800 MHz LO signal. The down-conversion mixer have been fabricated in Global Foundry 0.13 ?m CMOS technology. A suitable test bench is developed to measure the major performance parameters of the proposed design. At 1.0 V supply voltage, the mixer consumes 2.4 mW of power. Measurement results show 17 dB conversion gain (CG), 10 dB noise figure (NF), 11.3 dBm third-order intercept point (IIP3), and port-to-port isolation greater than 50 dB. A study on various Figure-of-Merit was conducted and a suitable Figure-of-Merit was selected to better characterize the proposed design.