Investigation of latch-up behaviour in 0.5 micron CMOS technology / Wan Fazlida Hanim Abdullah, Suhana Sulaiman and Mohd Jamil Napiah
The research project investigates available latch-up test structures from MIMOS Berhad and covers current-voltage characterization of silicon-controlled rectifier behaviour of parasitic BJTs in CMOS technology. Measurement setup utilizing the structures for IV measurements are designed. A suitable m...
| Main Authors: | , , |
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| Format: | Monograph |
| Language: | English |
| Published: |
Institute of Research, Development and Commercialization , Universiti Teknologi MARA
2005
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| Subjects: | |
| Online Access: | https://ir.uitm.edu.my/id/eprint/8030/ |
| _version_ | 1848802857697935360 |
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| author | Abdullah, Wan Fazlida Hanim Sulaiman, Suhana Sulaiman Napiah, Mohd Jamil |
| author_facet | Abdullah, Wan Fazlida Hanim Sulaiman, Suhana Sulaiman Napiah, Mohd Jamil |
| author_sort | Abdullah, Wan Fazlida Hanim |
| building | UiTM Institutional Repository |
| collection | Online Access |
| description | The research project investigates available latch-up test structures from MIMOS Berhad and covers current-voltage characterization of silicon-controlled rectifier behaviour of parasitic BJTs in CMOS technology. Measurement setup utilizing the structures for IV measurements are designed. A suitable measurement routine for the testing of latch-up in MOS device engineering at wafer level is developed for use in research environment.Tests are done on available MIMOS test structures representing twin tub technology and
silicon-on-insulator substrate using automatic semiconductor characterization system comprising of Semiconductor Parametric Characterization Software (SPECS), UFK200 automatic prober and Agilent 4073 tester. Avalanche induced latch-up of three types of device were demonstrated: SOI without thickness adjustment, SOI with thinner layer due to thickness adjustment and bulk silicon control device are demonstrated. Immunity towards latch-up is improved for devices on BSOI substrate. |
| first_indexed | 2025-11-14T21:30:01Z |
| format | Monograph |
| id | uitm-8030 |
| institution | Universiti Teknologi MARA |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-14T21:30:01Z |
| publishDate | 2005 |
| publisher | Institute of Research, Development and Commercialization , Universiti Teknologi MARA |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | uitm-80302024-12-06T02:32:52Z https://ir.uitm.edu.my/id/eprint/8030/ Investigation of latch-up behaviour in 0.5 micron CMOS technology / Wan Fazlida Hanim Abdullah, Suhana Sulaiman and Mohd Jamil Napiah Abdullah, Wan Fazlida Hanim Sulaiman, Suhana Sulaiman Napiah, Mohd Jamil Electronics The research project investigates available latch-up test structures from MIMOS Berhad and covers current-voltage characterization of silicon-controlled rectifier behaviour of parasitic BJTs in CMOS technology. Measurement setup utilizing the structures for IV measurements are designed. A suitable measurement routine for the testing of latch-up in MOS device engineering at wafer level is developed for use in research environment.Tests are done on available MIMOS test structures representing twin tub technology and silicon-on-insulator substrate using automatic semiconductor characterization system comprising of Semiconductor Parametric Characterization Software (SPECS), UFK200 automatic prober and Agilent 4073 tester. Avalanche induced latch-up of three types of device were demonstrated: SOI without thickness adjustment, SOI with thinner layer due to thickness adjustment and bulk silicon control device are demonstrated. Immunity towards latch-up is improved for devices on BSOI substrate. Institute of Research, Development and Commercialization , Universiti Teknologi MARA 2005 Monograph NonPeerReviewed text en https://ir.uitm.edu.my/id/eprint/8030/2/8030.pdf Abdullah, Wan Fazlida Hanim and Sulaiman, Suhana Sulaiman and Napiah, Mohd Jamil (2005) Investigation of latch-up behaviour in 0.5 micron CMOS technology / Wan Fazlida Hanim Abdullah, Suhana Sulaiman and Mohd Jamil Napiah. (2005) UNSPECIFIED. Institute of Research, Development and Commercialization , Universiti Teknologi MARA. <http://terminalib.uitm.edu.my/8030.pdf> (Submitted) |
| spellingShingle | Electronics Abdullah, Wan Fazlida Hanim Sulaiman, Suhana Sulaiman Napiah, Mohd Jamil Investigation of latch-up behaviour in 0.5 micron CMOS technology / Wan Fazlida Hanim Abdullah, Suhana Sulaiman and Mohd Jamil Napiah |
| title | Investigation of latch-up behaviour in 0.5 micron CMOS technology / Wan Fazlida Hanim Abdullah, Suhana Sulaiman and Mohd Jamil Napiah |
| title_full | Investigation of latch-up behaviour in 0.5 micron CMOS technology / Wan Fazlida Hanim Abdullah, Suhana Sulaiman and Mohd Jamil Napiah |
| title_fullStr | Investigation of latch-up behaviour in 0.5 micron CMOS technology / Wan Fazlida Hanim Abdullah, Suhana Sulaiman and Mohd Jamil Napiah |
| title_full_unstemmed | Investigation of latch-up behaviour in 0.5 micron CMOS technology / Wan Fazlida Hanim Abdullah, Suhana Sulaiman and Mohd Jamil Napiah |
| title_short | Investigation of latch-up behaviour in 0.5 micron CMOS technology / Wan Fazlida Hanim Abdullah, Suhana Sulaiman and Mohd Jamil Napiah |
| title_sort | investigation of latch-up behaviour in 0.5 micron cmos technology / wan fazlida hanim abdullah, suhana sulaiman and mohd jamil napiah |
| topic | Electronics |
| url | https://ir.uitm.edu.my/id/eprint/8030/ |