Logical effort base adder circuits transistor sizing using constriction factor and mutative variants of particle swarm optimization algorithm / Muhammad Aiman Johari

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Logical effort base adder circuits transistor sizing using constriction factor and mutative variants of particle swarm optimization algorithm / Muhammad Aiman Johari

In Semiconductor world, the design and fabrication of Integrated Circuit (IC) associated with development time, operating speed and power requirements. The goodness of each design must be evaluated before it is chosen, especially on speed of the circuits where it represent the time taken to execute...

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Bibliographic Details
Main Author:	Johari, Muhammad Aiman
Format:	Thesis
Language:	English
Published:	2015
Subjects:	Microelectronics
Online Access:	https://ir.uitm.edu.my/id/eprint/21626/

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