Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform
A lifting-based VLSI architecture for two-dimensional discrete wavelet transform (2-D DWT) for 5/3 and 9/7 algorithms, called, pipelined intermediate architecture was proposed by Ibrahim et al., which aim at reducing power consumption of the overlapped external memory access without using the expens...
| Main Authors: | , |
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| Format: | Citation Index Journal |
| Language: | English |
| Published: |
2009
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| Subjects: | |
| Online Access: | http://scholars.utp.edu.my/id/eprint/417/ http://scholars.utp.edu.my/id/eprint/417/1/paper.pdf |
| _version_ | 1848658980620992512 |
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| author | Koko I., Saeed H., Agustiawan |
| author_facet | Koko I., Saeed H., Agustiawan |
| author_sort | Koko I., Saeed |
| building | UTP Institutional Repository |
| collection | Online Access |
| description | A lifting-based VLSI architecture for two-dimensional discrete wavelet transform (2-D DWT) for 5/3 and 9/7 algorithms, called, pipelined intermediate architecture was proposed by Ibrahim et al., which aim at reducing power consumption of the overlapped external memory access without using the expensive line-buffer. In this paper, we explore parallelism in order to best meet real-time applications of 2-D DWT with demanding requirements in terms of speed, throughput, and power consumption. Therefore, 2-parallel and 3-parallel form of the single pipelined intermediate architecture are proposed. The 2-parallel and 3-parallel pipelined intermediate architectures achieve speedup factors of 2 and 3, respectively, as compared with single pipelined intermediate architecture proposed by Ibrahim et al.
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| first_indexed | 2025-11-13T07:23:09Z |
| format | Citation Index Journal |
| id | oai:scholars.utp.edu.my:417 |
| institution | Universiti Teknologi Petronas |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-13T07:23:09Z |
| publishDate | 2009 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | oai:scholars.utp.edu.my:4172017-01-19T08:25:45Z http://scholars.utp.edu.my/id/eprint/417/ Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform Koko I., Saeed H., Agustiawan TK Electrical engineering. Electronics Nuclear engineering A lifting-based VLSI architecture for two-dimensional discrete wavelet transform (2-D DWT) for 5/3 and 9/7 algorithms, called, pipelined intermediate architecture was proposed by Ibrahim et al., which aim at reducing power consumption of the overlapped external memory access without using the expensive line-buffer. In this paper, we explore parallelism in order to best meet real-time applications of 2-D DWT with demanding requirements in terms of speed, throughput, and power consumption. Therefore, 2-parallel and 3-parallel form of the single pipelined intermediate architecture are proposed. The 2-parallel and 3-parallel pipelined intermediate architectures achieve speedup factors of 2 and 3, respectively, as compared with single pipelined intermediate architecture proposed by Ibrahim et al. 2009 Citation Index Journal NonPeerReviewed application/pdf en http://scholars.utp.edu.my/id/eprint/417/1/paper.pdf Koko I., Saeed and H., Agustiawan (2009) Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform. [Citation Index Journal] http://www.scopus.com/inward/record.url?eid=2-s2.0-67649405062&partnerID=40&md5=9954a40f8f88f1033facc22319738b8d |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Koko I., Saeed H., Agustiawan Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform |
| title | Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform
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| title_full | Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform
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| title_fullStr | Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform
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| title_full_unstemmed | Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform
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| title_short | Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform
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| title_sort | parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://scholars.utp.edu.my/id/eprint/417/ http://scholars.utp.edu.my/id/eprint/417/ http://scholars.utp.edu.my/id/eprint/417/1/paper.pdf |