Optimization of Processor Architecture for Image Edge Detection Filter
In this paper, a dedicated edge detection processor architecture based on field programmable gate arrays is presented. The architecture is an optimization of the Sobel edge detection filter, specifically focusing on the reduction of the computation time. The proposed architecture reduces the number...
| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2010
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| Subjects: | |
| Online Access: | http://scholars.utp.edu.my/id/eprint/2089/ http://scholars.utp.edu.my/id/eprint/2089/1/Cambridg_paper_-_final_version.pdf |
| _version_ | 1848659201745747968 |
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| author | M. Osman, Zahraa Elhassan Hussin, Fawnizu Azmadi Zain Ali, Noohul Basheer |
| author_facet | M. Osman, Zahraa Elhassan Hussin, Fawnizu Azmadi Zain Ali, Noohul Basheer |
| author_sort | M. Osman, Zahraa Elhassan |
| building | UTP Institutional Repository |
| collection | Online Access |
| description | In this paper, a dedicated edge detection processor architecture based on field programmable gate arrays is presented. The architecture is an optimization of the Sobel edge detection filter, specifically focusing on the reduction of the computation time. The proposed architecture reduces the number of calculations required for the edge detection process by enhancing the data reuse, i.e. minimizing the frequency of memory access. Direct hardware implementation as proposed by previous works require most image pixels to be read from memory up to six times and transferred into the Sobel edge detection processor. In our work, we try to reduce the number of pixels read therefore affecting tremendous potential speed suitable for the embedded video processing applications. |
| first_indexed | 2025-11-13T07:26:40Z |
| format | Conference or Workshop Item |
| id | oai:scholars.utp.edu.my:2089 |
| institution | Universiti Teknologi Petronas |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-13T07:26:40Z |
| publishDate | 2010 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | oai:scholars.utp.edu.my:20892017-01-19T08:24:22Z http://scholars.utp.edu.my/id/eprint/2089/ Optimization of Processor Architecture for Image Edge Detection Filter M. Osman, Zahraa Elhassan Hussin, Fawnizu Azmadi Zain Ali, Noohul Basheer QA75 Electronic computers. Computer science In this paper, a dedicated edge detection processor architecture based on field programmable gate arrays is presented. The architecture is an optimization of the Sobel edge detection filter, specifically focusing on the reduction of the computation time. The proposed architecture reduces the number of calculations required for the edge detection process by enhancing the data reuse, i.e. minimizing the frequency of memory access. Direct hardware implementation as proposed by previous works require most image pixels to be read from memory up to six times and transferred into the Sobel edge detection processor. In our work, we try to reduce the number of pixels read therefore affecting tremendous potential speed suitable for the embedded video processing applications. 2010-03-24 Conference or Workshop Item PeerReviewed application/pdf en http://scholars.utp.edu.my/id/eprint/2089/1/Cambridg_paper_-_final_version.pdf M. Osman, Zahraa Elhassan and Hussin, Fawnizu Azmadi and Zain Ali, Noohul Basheer (2010) Optimization of Processor Architecture for Image Edge Detection Filter. In: 12th International Conference on Modelling and Simulation (UMSim), 24-26 March 2010, Cambdridge, UK. http://dx.doi.org/10.1109/UKSIM.2010.123 |
| spellingShingle | QA75 Electronic computers. Computer science M. Osman, Zahraa Elhassan Hussin, Fawnizu Azmadi Zain Ali, Noohul Basheer Optimization of Processor Architecture for Image Edge Detection Filter |
| title | Optimization of Processor Architecture for Image Edge Detection Filter |
| title_full | Optimization of Processor Architecture for Image Edge Detection Filter |
| title_fullStr | Optimization of Processor Architecture for Image Edge Detection Filter |
| title_full_unstemmed | Optimization of Processor Architecture for Image Edge Detection Filter |
| title_short | Optimization of Processor Architecture for Image Edge Detection Filter |
| title_sort | optimization of processor architecture for image edge detection filter |
| topic | QA75 Electronic computers. Computer science |
| url | http://scholars.utp.edu.my/id/eprint/2089/ http://scholars.utp.edu.my/id/eprint/2089/ http://scholars.utp.edu.my/id/eprint/2089/1/Cambridg_paper_-_final_version.pdf |