A method of realizing XOR/XNOR gate using symmetric boolean function lattice structure
The current CMOS’s industry standard XOR and XNOR gate consist of 12 and 10 transistors, respectively. This transistor count could be lowered down to produce low power circuits as XOR/XNOR are extensively used in many functional modules. As a solution, a method for realizing low transistor count X...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Penerbit Universiti Kebangsaan Malaysia
2021
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| Online Access: | http://journalarticle.ukm.my/19093/ http://journalarticle.ukm.my/19093/1/13.pdf |
| _version_ | 1848814747204452352 |
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| author | Muhazam Mustapha, Jeffery Lee, Anis Shahida Niza Mokhtar, Kamarul ‘Asyikin Mustafa, Bakhtiar Affendi Rosdi, |
| author_facet | Muhazam Mustapha, Jeffery Lee, Anis Shahida Niza Mokhtar, Kamarul ‘Asyikin Mustafa, Bakhtiar Affendi Rosdi, |
| author_sort | Muhazam Mustapha, |
| building | UKM Institutional Repository |
| collection | Online Access |
| description | The current CMOS’s industry standard XOR and XNOR gate consist of 12 and 10 transistors, respectively. This transistor
count could be lowered down to produce low power circuits as XOR/XNOR are extensively used in many functional
modules. As a solution, a method for realizing low transistor count XOR/XNOR gates using a special property of
symmetric Boolean function is proposed. This property suggests that the circuits for such functions can be realized with
fewer transistors using a special lattice structure circuit. Modifications are made to the original lattice structure to
match with the current CMOS technology requirements. The final circuits require eight transistors each for XOR/XNOR
with mixtures of NMOS and PMOS at push-up and pull-down networks. Simulations show that the intended logic functions
of XOR/XNOR are achieved. The reading of actual voltage swing, however, shows that the output is either 0.3 V over
ground or below VDD when there is a mixture of NMOS and PMOS as pull-down or push-up networks, respectively. More
voltage loss of 0.4 V is observed if only NMOS is at push-up or only PMOS is at pull-down networks. As a preliminary
work, this achievement of the functional logic level warrants more future work to improve the loss in output voltage
swing. |
| first_indexed | 2025-11-15T00:39:00Z |
| format | Article |
| id | oai:generic.eprints.org:19093 |
| institution | Universiti Kebangasaan Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T00:39:00Z |
| publishDate | 2021 |
| publisher | Penerbit Universiti Kebangsaan Malaysia |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | oai:generic.eprints.org:190932022-07-26T04:35:09Z http://journalarticle.ukm.my/19093/ A method of realizing XOR/XNOR gate using symmetric boolean function lattice structure Muhazam Mustapha, Jeffery Lee, Anis Shahida Niza Mokhtar, Kamarul ‘Asyikin Mustafa, Bakhtiar Affendi Rosdi, The current CMOS’s industry standard XOR and XNOR gate consist of 12 and 10 transistors, respectively. This transistor count could be lowered down to produce low power circuits as XOR/XNOR are extensively used in many functional modules. As a solution, a method for realizing low transistor count XOR/XNOR gates using a special property of symmetric Boolean function is proposed. This property suggests that the circuits for such functions can be realized with fewer transistors using a special lattice structure circuit. Modifications are made to the original lattice structure to match with the current CMOS technology requirements. The final circuits require eight transistors each for XOR/XNOR with mixtures of NMOS and PMOS at push-up and pull-down networks. Simulations show that the intended logic functions of XOR/XNOR are achieved. The reading of actual voltage swing, however, shows that the output is either 0.3 V over ground or below VDD when there is a mixture of NMOS and PMOS as pull-down or push-up networks, respectively. More voltage loss of 0.4 V is observed if only NMOS is at push-up or only PMOS is at pull-down networks. As a preliminary work, this achievement of the functional logic level warrants more future work to improve the loss in output voltage swing. Penerbit Universiti Kebangsaan Malaysia 2021 Article PeerReviewed application/pdf en http://journalarticle.ukm.my/19093/1/13.pdf Muhazam Mustapha, and Jeffery Lee, and Anis Shahida Niza Mokhtar, and Kamarul ‘Asyikin Mustafa, and Bakhtiar Affendi Rosdi, (2021) A method of realizing XOR/XNOR gate using symmetric boolean function lattice structure. Jurnal Kejuruteraan, 4 (2(SI)). pp. 85-92. ISSN 0128-0198 https://www.ukm.my/jkukm/si-42-2021/ |
| spellingShingle | Muhazam Mustapha, Jeffery Lee, Anis Shahida Niza Mokhtar, Kamarul ‘Asyikin Mustafa, Bakhtiar Affendi Rosdi, A method of realizing XOR/XNOR gate using symmetric boolean function lattice structure |
| title | A method of realizing XOR/XNOR gate using symmetric boolean function lattice structure |
| title_full | A method of realizing XOR/XNOR gate using symmetric boolean function lattice structure |
| title_fullStr | A method of realizing XOR/XNOR gate using symmetric boolean function lattice structure |
| title_full_unstemmed | A method of realizing XOR/XNOR gate using symmetric boolean function lattice structure |
| title_short | A method of realizing XOR/XNOR gate using symmetric boolean function lattice structure |
| title_sort | method of realizing xor/xnor gate using symmetric boolean function lattice structure |
| url | http://journalarticle.ukm.my/19093/ http://journalarticle.ukm.my/19093/ http://journalarticle.ukm.my/19093/1/13.pdf |